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| author | Connor Abbott <cwabbott0@gmail.com> | 2023-12-07 21:30:48 +0000 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2023-12-10 10:19:18 -0800 |
| commit | 44a88fa45665318473bfdbb832eba1da2d0a3740 (patch) | |
| tree | 0ccf5dcdb84bc570263f0922aa2b1f4c6a3cfdf6 | |
| parent | 8814455a0e54ca353b4b0ad5105569d3fdb945cc (diff) | |
| download | linux-44a88fa45665318473bfdbb832eba1da2d0a3740.tar.gz linux-44a88fa45665318473bfdbb832eba1da2d0a3740.tar.bz2 linux-44a88fa45665318473bfdbb832eba1da2d0a3740.zip | |
drm/msm: Add param for the highest bank bit
This parameter is programmed by the kernel and influences the tiling
layout of images. Exposing it to userspace will allow it to tile/untile
images correctly without guessing what value the kernel programmed, and
allow us to change it in the future without breaking userspace.
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/571181/
Signed-off-by: Rob Clark <robdclark@chromium.org>
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 | ||||
| -rw-r--r-- | include/uapi/drm/msm_drm.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 3fe9fd240cc7..074fb498706f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -373,6 +373,9 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, return -EINVAL; *value = ctx->aspace->va_size; return 0; + case MSM_PARAM_HIGHEST_BANK_BIT: + *value = adreno_gpu->ubwc_config.highest_bank_bit; + return 0; default: DBG("%s: invalid param: %u", gpu->name, param); return -EINVAL; diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index 6f2a7ad04aa4..d8a6b3472760 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -86,6 +86,7 @@ struct drm_msm_timespec { #define MSM_PARAM_CMDLINE 0x0d /* WO: override for task cmdline */ #define MSM_PARAM_VA_START 0x0e /* RO: start of valid GPU iova range */ #define MSM_PARAM_VA_SIZE 0x0f /* RO: size of valid GPU iova range (bytes) */ +#define MSM_PARAM_HIGHEST_BANK_BIT 0x10 /* RO */ /* For backwards compat. The original support for preemption was based on * a single ring per priority level so # of priority levels equals the # |