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authorAlex Deucher <alexander.deucher@amd.com>2017-03-02 16:31:08 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-03-29 23:54:20 -0400
commit4adc5ab813eaf57fe4027ea93fcc91182f613495 (patch)
treed7f07599a8b510b0d3d0fd017c03fb8041ab202b
parent7fee1fd93b105e8ab7a89960097bb6c17aab0e52 (diff)
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drm/amdgpu: Add the DCE 12.0 register headers
These are the register headers for the Display and Composition Engine on vega10. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h9868
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h18193
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h64636
3 files changed, 92697 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h
new file mode 100644
index 000000000000..8a0007ce43dc
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h
@@ -0,0 +1,9868 @@
+/*
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dce_12_0_DEFAULT_HEADER
+#define _dce_12_0_DEFAULT_HEADER
+
+
+// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
+#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
+#define mmdispdec_VGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_perfmon0_dispdec
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON0_PERFCOUNTER_STATE_DEFAULT 0x00000000
+#define mmDC_PERFMON0_PERFMON_CNTL_DEFAULT 0x00000100
+#define mmDC_PERFMON0_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+#define mmDC_PERFMON0_PERFMON_HI_DEFAULT 0x00000000
+#define mmDC_PERFMON0_PERFMON_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_perfmon13_dispdec
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON13_PERFCOUNTER_STATE_DEFAULT 0x00000000
+#define mmDC_PERFMON13_PERFMON_CNTL_DEFAULT 0x00000100
+#define mmDC_PERFMON13_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+#define mmDC_PERFMON13_PERFMON_HI_DEFAULT 0x00000000
+#define mmDC_PERFMON13_PERFMON_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_displaypllregs_dispdec
+#define mmPPLL_VREG_CFG_DEFAULT 0x00000000
+#define mmPPLL_MODE_CNTL_DEFAULT 0x00020100
+#define mmPPLL_FREQ_CTRL0_DEFAULT 0x00280000
+#define mmPPLL_FREQ_CTRL1_DEFAULT 0x00000000
+#define mmPPLL_FREQ_CTRL2_DEFAULT 0x00000000
+#define mmPPLL_FREQ_CTRL3_DEFAULT 0x00190040
+#define mmPPLL_BW_CTRL_COARSE_DEFAULT 0x0020c4b1
+#define mmPPLL_BW_CTRL_FINE_DEFAULT 0x00000001
+#define mmPPLL_CAL_CTRL_DEFAULT 0x64000002
+#define mmPPLL_LOOP_CTRL_DEFAULT 0x00000090
+#define mmPPLL_REFCLK_CNTL_DEFAULT 0x00018004
+#define mmPPLL_CLKOUT_CNTL_DEFAULT 0x00022500
+#define mmPPLL_DFT_CNTL_DEFAULT 0x00000004
+#define mmPPLL_ANALOG_CNTL_DEFAULT 0x00000000
+#define mmPPLL_POSTDIV_DEFAULT 0x00000400
+#define mmPPLL_OBSERVE0_DEFAULT 0x00000000
+#define mmPPLL_OBSERVE1_DEFAULT 0x04b00000
+#define mmPPLL_UPDATE_CNTL_DEFAULT 0x00000000
+#define mmPPLL_OBSERVE0_OUT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dccg_pll0_dispdec
+#define mmPLL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000
+#define mmPLL_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_perfmon1_dispdec
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON1_PERFCOUNTER_STATE_DEFAULT 0x00000000
+#define mmDC_PERFMON1_PERFMON_CNTL_DEFAULT 0x00000100
+#define mmDC_PERFMON1_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+#define mmDC_PERFMON1_PERFMON_HI_DEFAULT 0x00000000
+#define mmDC_PERFMON1_PERFMON_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_mcif_wb0_dispdec
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400
+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000
+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040
+#define mmMCIF_WB0_MCIF_WB_WATERMARK_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000
+#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002
+#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080
+#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff
+#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff
+
+
+// addressBlock: dce_dc_mcif_wb1_dispdec
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400
+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000
+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040
+#define mmMCIF_WB1_MCIF_WB_WATERMARK_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000
+#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002
+#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080
+#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff
+#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff
+
+
+// addressBlock: dce_dc_mcif_wb2_dispdec
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400
+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000
+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040
+#define mmMCIF_WB2_MCIF_WB_WATERMARK_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000
+#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000
+#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002
+#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080
+#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff
+#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff
+
+
+// addressBlock: dce_dc_cwb0_dispdec
+#define mmCWB0_CWB_CTRL_DEFAULT 0x00000110
+#define mmCWB0_CWB_FENCE_PAR0_DEFAULT 0x03ff03ff
+#define mmCWB0_CWB_FENCE_PAR1_DEFAULT 0x000102ff
+#define mmCWB0_CWB_CRC_CTRL_DEFAULT 0x00000000
+#define mmCWB0_CWB_CRC_RED_GREEN_MASK_DEFAULT 0xffffffff
+#define mmCWB0_CWB_CRC_BLUE_MASK_DEFAULT 0x0000ffff
+#define mmCWB0_CWB_CRC_RED_GREEN_RESULT_DEFAULT 0x00000000
+#define mmCWB0_CWB_CRC_BLUE_RESULT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_cwb1_dispdec
+#define mmCWB1_CWB_CTRL_DEFAULT 0x00000110
+#define mmCWB1_CWB_FENCE_PAR0_DEFAULT 0x03ff03ff
+#define mmCWB1_CWB_FENCE_PAR1_DEFAULT 0x000102ff
+#define mmCWB1_CWB_CRC_CTRL_DEFAULT 0x00000000
+#define mmCWB1_CWB_CRC_RED_GREEN_MASK_DEFAULT 0xffffffff
+#define mmCWB1_CWB_CRC_BLUE_MASK_DEFAULT 0x0000ffff
+#define mmCWB1_CWB_CRC_RED_GREEN_RESULT_DEFAULT 0x00000000
+#define mmCWB1_CWB_CRC_BLUE_RESULT_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dc_perfmon9_dispdec
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL_DEFAULT 0x00000000
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON9_PERFCOUNTER_STATE_DEFAULT 0x00000000
+#define mmDC_PERFMON9_PERFMON_CNTL_DEFAULT 0x00000100
+#define mmDC_PERFMON9_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000
+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_DEFAULT 0x00000000
+#define mmDC_PERFMON9_PERFMON_HI_DEFAULT 0x00000000
+#define mmDC_PERFMON9_PERFMON_LOW_DEFAULT 0x00000000
+
+
+// addressBlock: dce_dc_dispdec
+#define mmVGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000
+#define mmVGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000
+#define mmVGA_RENDER_CONTROL_DEFAULT 0x0000000f
+#define mmVGA_SEQUENCER_RESET_CONTROL_DEFAULT 0x00003f3f
+#define mmVGA_MODE_CONTROL_DEFAULT 0x00000000
+#define mmVGA_SURFACE_PITCH_SELECT_DEFAULT 0x00000002
+#define mmVGA_MEMORY_BASE_ADDRESS_DEFAULT 0x00000000
+#define mmVGA_DISPBUF1_SURFACE_ADDR_DEFAULT 0x00000000
+#define mmVGA_DISPBUF2_SURFACE_ADDR_DEFAULT 0x00000000
+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_DEFAULT 0x00000000
+#define mmVGA_HDP_CONTROL_DEFAULT 0x00000000
+#define mmVGA_CACHE_CONTROL_DEFAULT 0x00000000
+#define mmD1VGA_CONTROL_DEFAULT 0x00000000
+#define mmD2VGA_CONTROL_DEFAULT 0x00000000
+#define mmVGA_STATUS_DEFAULT 0x00000000
+#define mmVGA_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmVGA_STATUS_CLEAR_DEFAULT 0x00000000
+#define mmVGA_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmVGA_MAIN_CONTROL_DEFAULT 0x00005018
+#define mmVGA_TEST_CONTROL_DEFAULT 0x00000000
+#define mmVGA_QOS_CTRL_DEFAULT 0x00000000
+#define mmCRTC8_IDX_DEFAULT 0x00000000
+#define mmCRTC8_DATA_DEFAULT 0x00000000
+#define mmGENFC_WT_DEFAULT 0x00000000
+#define mmGENS1_DEFAULT 0x00000000
+#define mmATTRDW_DEFAULT 0x00000000
+#define mmATTRX_DEFAULT 0x00000000
+#define mmATTRDR_DEFAULT 0x00000000
+#define mmGENMO_WT_DEFAULT 0x00000000
+#define mmGENS0_DEFAULT 0x00000000
+#define mmGENENB_DEFAULT 0x00000000
+#define mmSEQ8_IDX_DEFAULT 0x00000000
+#define mmSEQ8_DATA_DEFAULT 0x00000000
+#define mmDAC_MASK_DEFAULT 0x00000000
+#define mmDAC_R_INDEX_DEFAULT 0x00000000
+#define mmDAC_W_INDEX_DEFAULT 0x00000000
+#define mmDAC_DATA_DEFAULT 0x00000000
+#define mmGENFC_RD_DEFAULT 0x00000000
+#define mmGENMO_RD_DEFAULT 0x00000000
+#define mmGRPH8_IDX_DEFAULT 0x00000000
+#define mmGRPH8_DATA_DEFAULT 0x00000000
+#define mmCRTC8_IDX_1_DEFAULT 0x00000000
+#define mmCRTC8_DATA_1_DEFAULT 0x00000000
+#define mmGENFC_WT_1_DEFAULT 0x00000000
+#define mmGENS1_1_DEFAULT 0x00000000
+#define mmD3VGA_CONTROL_DEFAULT 0x00000000
+#define mmD4VGA_CONTROL_DEFAULT 0x00000000
+#define mmD5VGA_CONTROL_DEFAULT 0x00000000
+#define mmD6VGA_CONTROL_DEFAULT 0x00000000
+#define mmVGA_SOURCE_SELECT_DEFAULT 0x00000100
+#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmSYMCLKLPA_CLOCK_ENABLE_DEFAULT 0x00000000
+#define mmSYMCLKLPB_CLOCK_ENABLE_DEFAULT 0x00000100
+#define mmDPREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
+#define mmREFCLK_CNTL_DEFAULT 0x00000000
+#define mmMIPI_CLK_CNTL_DEFAULT 0x00000000
+#define mmREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
+#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmDCCG_PERFMON_CNTL2_DEFAULT 0x00000000
+#define mmDSICLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
+#define mmDCCG_CBUS_WRCMD_DELAY_DEFAULT 0x00000003
+#define mmDCCG_DS_DTO_INCR_DEFAULT 0x00000000
+#define mmDCCG_DS_DTO_MODULO_DEFAULT 0x00000000
+#define mmDCCG_DS_CNTL_DEFAULT 0x00000000
+#define mmDCCG_DS_HW_CAL_INTERVAL_DEFAULT 0x00989680
+#define mmSYMCLKG_CLOCK_ENABLE_DEFAULT 0x00000600
+#define mmDPREFCLK_CNTL_DEFAULT 0x00000000
+#define mmAOMCLK0_CNTL_DEFAULT 0x00000000
+#define mmAOMCLK1_CNTL_DEFAULT 0x00000000
+#define mmAOMCLK2_CNTL_DEFAULT 0x00000000
+#define mmDCCG_AUDIO_DTO2_PHASE_DEFAULT 0x00000000
+#define mmDCCG_AUDIO_DTO2_MODULO_DEFAULT 0x00000001
+#define mmDCE_VERSION_DEFAULT 0x00000000
+#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmDCCG_GTC_CNTL_DEFAULT 0x00000000
+#define mmDCCG_GTC_DTO_INCR_DEFAULT 0x00000000
+#define mmDCCG_GTC_DTO_MODULO_DEFAULT 0x00000000
+#define mmDCCG_GTC_CURRENT_DEFAULT 0x00000000
+#define mmDENTIST_DISPCLK_CNTL_DEFAULT 0x64010064
+#define mmMIPI_DTO_CNTL_DEFAULT 0x00000000
+#define mmMIPI_DTO_PHASE_DEFAULT 0x00000000
+#define mmMIPI_DTO_MODULO_DEFAULT 0x00000000
+#define mmDAC_CLK_ENABLE_DEFAULT 0x00000000
+#define mmDVO_CLK_ENABLE_DEFAULT 0x00000000
+#define mmAVSYNC_COUNTER_WRITE_DEFAULT 0x00000000
+#define mmAVSYNC_COUNTER_CONTROL_DEFAULT 0x00000000
+#define mmDMCU_SMU_INTERRUPT_CNTL_DEFAULT 0x00000000
+#define mmSMU_CONTROL_DEFAULT 0x00000000
+#define mmSMU_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmAVSYNC_COUNTER_READ_DEFAULT 0x00000000
+#define mmMILLISECOND_TIME_BASE_DIV_DEFAULT 0x001186a0
+#define mmDISPCLK_FREQ_CHANGE_CNTL_DEFAULT 0x08010028
+#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_DEFAULT 0x00000001
+#define mmDCCG_PERFMON_CNTL_DEFAULT 0xfffff800
+#define mmDCCG_GATE_DISABLE_CNTL_DEFAULT 0x74ee00fd
+#define mmDISPCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
+#define mmSCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
+#define mmDCCG_CAC_STATUS_DEFAULT 0x00000000
+#define mmPIXCLK1_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmPIXCLK2_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmPIXCLK0_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmMICROSECOND_TIME_BASE_DIV_DEFAULT 0x00120464
+#define mmDCCG_GATE_DISABLE_CNTL2_DEFAULT 0x037f037f
+#define mmSYMCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200
+#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000
+#define mmDCCG_DISP_CNTL_REG_DEFAULT 0x00000000
+#define mmCRTC0_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP_DTO0_PHASE_DEFAULT 0x00000000
+#define mmDP_DTO0_MODULO_DEFAULT 0x00000000
+#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmCRTC1_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP_DTO1_PHASE_DEFAULT 0x00000000
+#define mmDP_DTO1_MODULO_DEFAULT 0x00000000
+#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmCRTC2_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP_DTO2_PHASE_DEFAULT 0x00000000
+#define mmDP_DTO2_MODULO_DEFAULT 0x00000000
+#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmCRTC3_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP_DTO3_PHASE_DEFAULT 0x00000000
+#define mmDP_DTO3_MODULO_DEFAULT 0x00000000
+#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmCRTC4_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP_DTO4_PHASE_DEFAULT 0x00000000
+#define mmDP_DTO4_MODULO_DEFAULT 0x00000000
+#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmCRTC5_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmDP_DTO5_PHASE_DEFAULT 0x00000000
+#define mmDP_DTO5_MODULO_DEFAULT 0x00000000
+#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000
+#define mmDCCG_SOFT_RESET_DEFAULT 0x00000000
+#define mmSYMCLKA_CLOCK_ENABLE_DEFAULT 0x00000000
+#define mmSYMCLKB_CLOCK_ENABLE_DEFAULT 0x00000100
+#define mmSYMCLKC_CLOCK_ENABLE_DEFAULT 0x00000200
+#define mmSYMCLKD_CLOCK_ENABLE_DEFAULT 0x00000300
+#define mmSYMCLKE_CLOCK_ENABLE_DEFAULT 0x00000400
+#define mmSYMCLKF_CLOCK_ENABLE_DEFAULT 0x00000500
+#define mmDVOACLKD_CNTL_DEFAULT 0x00070000
+#define mmDVOACLKC_MVP_CNTL_DEFAULT 0x00030000
+#define mmDVOACLKC_CNTL_DEFAULT 0x00030000
+#define mmDCCG_AUDIO_DTO_SOURCE_DEFAULT 0x00000030
+#define mmDCCG_AUDIO_DTO0_PHASE_DEFAULT 0x00000000
+#define mmDCCG_AUDIO_DTO0_MODULE_DEFAULT 0x00000001
+#define mmDCCG_AUDIO_DTO1_PHASE_DEFAULT 0x00000000
+#define mmDCCG_AUDIO_DTO1_MODULE_DEFAULT 0x00000001
+#define mmDCCG_TEST_CLK_SEL_DEFAULT 0x01ff01ff
+#define mmFBC_CNTL_DEFAULT 0x00000500
+#define mmFBC_IDLE_FORCE_CLEAR_MASK_DEFAULT 0x00000000
+#define mmFBC_START_STOP_DELAY_DEFAULT 0x00000000
+#define mmFBC_COMP_CNTL_DEFAULT 0x0000000f
+#define mmFBC_COMP_MODE_DEFAULT 0x00000000
+#define mmFBC_IND_LUT0_DEFAULT 0x00000000
+#define mmFBC_IND_LUT1_DEFAULT 0x00000000
+#define mmFBC_IND_LUT2_DEFAULT 0x00000000
+#define mmFBC_IND_LUT3_DEFAULT 0x00000000
+#define mmFBC_IND_LUT4_DEFAULT 0x00000000
+#define mmFBC_IND_LUT5_DEFAULT 0x00000000
+#define mmFBC_IND_LUT6_DEFAULT 0x00000000
+#define mmFBC_IND_LUT7_DEFAULT 0x00000000
+#define mmFBC_IND_LUT8_DEFAULT 0x00000000
+#define mmFBC_IND_LUT9_DEFAULT 0x00000000
+#define mmFBC_IND_LUT10_DEFAULT 0x00000000
+#define mmFBC_IND_LUT11_DEFAULT 0x00000000
+#define mmFBC_IND_LUT12_DEFAULT 0x00000000
+#define mmFBC_IND_LUT13_DEFAULT 0x00000000
+#define mmFBC_IND_LUT14_DEFAULT 0x00000000
+#define mmFBC_IND_LUT15_DEFAULT 0x00000000
+#define mmFBC_CSM_REGION_OFFSET_01_DEFAULT 0x00000000
+#define mmFBC_CSM_REGION_OFFSET_23_DEFAULT 0x00000000
+#define mmFBC_CLIENT_REGION_MASK_DEFAULT 0x00000000
+#define mmFBC_DEBUG_COMP_DEFAULT 0x00000000
+#define mmFBC_MISC_DEFAULT 0x0c306008
+#define mmFBC_STATUS_DEFAULT 0x00000000
+#define mmFBC_ALPHA_CNTL_DEFAULT 0x00000000
+#define mmFBC_ALPHA_RGB_OVERRIDE_DEFAULT 0x00000000
+#define mmPIPE0_PG_CONFIG_DEFAULT 0x00000001
+#define mmPIPE0_PG_ENABLE_DEFAULT 0x00000000
+#define mmPIPE0_PG_STATUS_DEFAULT 0x00000000
+#define mmPIPE1_PG_CONFIG_DEFAULT 0x00000001
+#define mmPIPE1_PG_ENABLE_DEFAULT 0x00000000
+#define mmPIPE1_PG_STATUS_DEFAULT 0x00000000
+#define mmPIPE2_PG_CONFIG_DEFAULT 0x00000001
+#define mmPIPE2_PG_ENABLE_DEFAULT 0x00000000
+#define mmPIPE2_PG_STATUS_DEFAULT 0x00000000
+#define mmPIPE3_PG_CONFIG_DEFAULT 0x00000001
+#define mmPIPE3_PG_ENABLE_DEFAULT 0x00000000
+#define mmPIPE3_PG_STATUS_DEFAULT 0x00000000
+#define mmPIPE4_PG_CONFIG_DEFAULT 0x00000001
+#define mmPIPE4_PG_ENABLE_DEFAULT 0x00000000
+#define mmPIPE4_PG_STATUS_DEFAULT 0x00000000
+#define mmPIPE5_PG_CONFIG_DEFAULT 0x00000001
+#define mmPIPE5_PG_ENABLE_DEFAULT 0x00000000
+#define mmPIPE5_PG_STATUS_DEFAULT 0x00000000
+#define mmDSI_PG_CONFIG_DEFAULT 0x00000001
+#define mmDSI_PG_ENABLE_DEFAULT 0x00000000
+#define mmDSI_PG_STATUS_DEFAULT 0x00000000
+#define mmDCFEV0_PG_CONFIG_DEFAULT 0x00000001
+#define mmDCFEV0_PG_ENABLE_DEFAULT 0x00000000
+#define mmDCFEV0_PG_STATUS_DEFAULT 0x00000000
+#define mmDCPG_INTERRUPT_STATUS_DEFAULT 0x00000000
+#define mmDCPG_INTERRUPT_CONTROL_DEFAULT 0x00000000
+#define mmDCPG_INTERRUPT_CONTROL2_DEFAULT 0x00000000
+#define mmDCFEV1_PG_CONFIG_DEFAULT 0x00000001
+#define mmDCFEV1_PG_ENABLE_DEFAULT 0x00000000
+#define mmDCFEV1_PG_STATUS_DEFAULT 0x00000000
+#define mmDC_IP_REQUEST_CNTL_DEFAULT 0x00000000
+#define mmDC_PGCNTL_STATUS_REG_DEFAULT 0x00000000
+#define mmDMIFV_STATUS_DEFAULT 0x00000000
+#define mmDMIF_CONTROL_DEFAULT 0x00000c04
+#define mmDMIF_STATUS_DEFAULT 0x0ff00000
+#define mmDMIF_ARBITRATION_CONTROL_DEFAULT 0x00042710
+#define mmPIPE0_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+#define mmPIPE1_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+#define mmPIPE2_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+#define mmPIPE3_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+#define mmPIPE4_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+#define mmPIPE5_ARBITRATION_CONTROL3_DEFAULT 0x00000000
+#define mmDMIF_P_VMID_DEFAULT 0x00000000
+#define mmDMIF_ADDR_CALC_DEFAULT 0x00000000
+#define mmDMIF_STATUS2_DEFAULT 0x00000000
+#define mmPIPE0_MAX_REQUESTS_DEFAULT 0x000003ff
+#defin