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| author | Dillon Varone <dillon.varone@amd.com> | 2024-08-01 15:35:51 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-08-13 10:44:39 -0400 |
| commit | 67ea53a4bd9d03a85eecd99875a2a794c886f788 (patch) | |
| tree | aaf4d272b2e5c1e3445f16905430406b154465bf | |
| parent | cc2991203c9d4e23051dbe5bcb1fc700fea26992 (diff) | |
| download | linux-67ea53a4bd9d03a85eecd99875a2a794c886f788.tar.gz linux-67ea53a4bd9d03a85eecd99875a2a794c886f788.tar.bz2 linux-67ea53a4bd9d03a85eecd99875a2a794c886f788.zip | |
drm/amd/display: Disable DCN401 UCLK P-State support on full updates
[WHY&HOW]
It is not guaranteed even for HW exclusive P-State methods (like
VActive) that P-state will be supported properly until optimize
bandwidth is called, so unconditionally disable it on full updates.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index b604c8886ef4..ac0a21ac318f 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1401,8 +1401,8 @@ void dcn401_prepare_bandwidth(struct dc *dc, bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support; unsigned int compbuf_size_kb = 0; - /* Any transition into or out of a FAMS config should disable MCLK switching first to avoid hangs */ - if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) { + /* Any transition into P-State support should disable MCLK switching first to avoid hangs */ + if (p_state_change_support) { dc->optimized_required = true; context->bw_ctx.bw.dcn.clk.p_state_change_support = false; } @@ -1441,7 +1441,7 @@ void dcn401_prepare_bandwidth(struct dc *dc, dcn401_fams2_global_control_lock(dc, context, false); } - if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) { + if (p_state_change_support != context->bw_ctx.bw.dcn.clk.p_state_change_support) { /* After disabling P-State, restore the original value to ensure we get the correct P-State * on the next optimize. */ context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support; |