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| author | Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> | 2023-06-24 10:28:38 +0530 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-07-07 13:51:47 -0400 |
| commit | 7c62129b415adbab283e5bddc619a749d7fe3163 (patch) | |
| tree | dfbb809523a1eb7a36fbeff27eb0e23c1347514f | |
| parent | a80fe1a698dcc7f5a493af9a16d516f8cbb20564 (diff) | |
| download | linux-7c62129b415adbab283e5bddc619a749d7fe3163.tar.gz linux-7c62129b415adbab283e5bddc619a749d7fe3163.tar.bz2 linux-7c62129b415adbab283e5bddc619a749d7fe3163.zip | |
drm/amd/display: Clean up warnings in amdgpu_dm_pp_smu.c
Fixes the following category of checkpatch warning:
WARNING: Block comments use a trailing */ on a separate line
+ * non-boosted one. */
WARNING: suspect code indent for conditional statements (8, 24)
+ if ((adev->asic_type >= CHIP_POLARIS10) &&
[...]
+ return true;
Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c index 75284e2cec74..848c5b4bb301 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c @@ -334,7 +334,8 @@ bool dm_pp_get_clock_levels_by_type( if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) { /* This clock is higher the validation clock. * Than means the previous one is the highest - * non-boosted one. */ + * non-boosted one. + */ DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n", dc_clks->num_levels, i); dc_clks->num_levels = i > 0 ? i : 1; @@ -406,10 +407,10 @@ bool dm_pp_notify_wm_clock_changes( * TODO: expand this to other ASICs */ if ((adev->asic_type >= CHIP_POLARIS10) && - (adev->asic_type <= CHIP_VEGAM) && - !amdgpu_dpm_set_watermarks_for_clocks_ranges(adev, - (void *)wm_with_clock_ranges)) - return true; + (adev->asic_type <= CHIP_VEGAM) && + !amdgpu_dpm_set_watermarks_for_clocks_ranges(adev, + (void *)wm_with_clock_ranges)) + return true; return false; } |