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| author | Sergey Matsievskiy <matsievskiysv@gmail.com> | 2024-09-25 21:44:16 +0300 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2024-10-02 15:11:07 +0200 |
| commit | 7f1f78b903c933617cbd352f9eafe9e3644f3b92 (patch) | |
| tree | 96df0f859c7a85d521002392545da097939f513a | |
| parent | 9e9c4666abb5bb444dac37e2d7eb5250c8d52a45 (diff) | |
| download | linux-7f1f78b903c933617cbd352f9eafe9e3644f3b92.tar.gz linux-7f1f78b903c933617cbd352f9eafe9e3644f3b92.tar.bz2 linux-7f1f78b903c933617cbd352f9eafe9e3644f3b92.zip | |
irqchip/ocelot: Comment sticky register clearing code
Add comment to the sticky register clearing code.
Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/all/20240925184416.54204-3-matsievskiysv@gmail.com
| -rw-r--r-- | drivers/irqchip/irq-mscc-ocelot.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c index c19ab379e8c5..3dc745b14caf 100644 --- a/drivers/irqchip/irq-mscc-ocelot.c +++ b/drivers/irqchip/irq-mscc-ocelot.c @@ -84,6 +84,12 @@ static void ocelot_irq_unmask(struct irq_data *data) u32 val; irq_gc_lock(gc); + /* + * Clear sticky bits for edge mode interrupts. + * Serval has only one trigger register replication, but the adjacent + * register is always read as zero, so there's no need to handle this + * case separately. + */ val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 0)) | irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 1)); if (!(val & mask)) |