isci: move core/controller to host

Now that the data structures are unified unify the implementation in
host.[ch] and cleanup namespace pollution.

Reported-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

28 files changed, 3360 insertions, 3940 deletions

diff --git a/drivers/scsi/isci/Makefile b/drivers/scsi/isci/Makefile
index 78ba0fc3548a..45f8f68caf4a 100644
--- a/drivers/scsi/isci/Makefile
+++ b/drivers/scsi/isci/Makefile
@@ -5,7 +5,6 @@ isci-objs := init.o phy.o request.o sata.o \
 	     host.o task.o probe_roms.o \
 	     remote_node_context.o \
 	     remote_node_table.o \
-	     core/scic_sds_controller.o  \
 	     core/scic_sds_request.o \
 	     core/scic_sds_stp_request.o \
 	     core/scic_sds_port.o \
diff --git a/drivers/scsi/isci/core/sci_util.c b/drivers/scsi/isci/core/sci_util.c
index 0101fec23865..595d8da1abba 100644
--- a/drivers/scsi/isci/core/sci_util.c
+++ b/drivers/scsi/isci/core/sci_util.c
@@ -55,7 +55,6 @@
 
 #include <linux/kernel.h>
 #include "sci_util.h"
-#include "sci_environment.h"
 #include "request.h"
 
 void *scic_request_get_virt_addr(struct scic_sds_request *sci_req, dma_addr_t phys_addr)
diff --git a/drivers/scsi/isci/core/scic_config_parameters.h b/drivers/scsi/isci/core/scic_config_parameters.h
index 8b8c9259f52f..15e7744dbdcf 100644
--- a/drivers/scsi/isci/core/scic_config_parameters.h
+++ b/drivers/scsi/isci/core/scic_config_parameters.h
@@ -229,44 +229,6 @@ union scic_oem_parameters {
 	struct scic_sds_oem_params sds1;
 };
 
-/**
- * scic_user_parameters_set() - This method allows the user to attempt to
- *    change the user parameters utilized by the controller.
- * @controller: This parameter specifies the controller on which to set the
- *    user parameters.
- * @user_parameters: This parameter specifies the USER_PARAMETERS object
- *    containing the potential new values.
- *
- * Indicate if the update of the user parameters was successful. SCI_SUCCESS
- * This value is returned if the operation succeeded. SCI_FAILURE_INVALID_STATE
- * This value is returned if the attempt to change the user parameter failed,
- * because changing one of the parameters is not currently allowed.
- * SCI_FAILURE_INVALID_PARAMETER_VALUE This value is returned if the user
- * supplied an invalid interrupt coalescence time, spin up delay interval, etc.
- */
-enum sci_status scic_user_parameters_set(
-	struct scic_sds_controller *controller,
-	union scic_user_parameters *user_parameters);
-
-/**
- * scic_oem_parameters_set() - This method allows the user to attempt to change
- *    the OEM parameters utilized by the controller.
- * @controller: This parameter specifies the controller on which to set the
- *    user parameters.
- * @oem_parameters: This parameter specifies the OEM parameters object
- *    containing the potential new values.
- *
- * Indicate if the update of the user parameters was successful. SCI_SUCCESS
- * This value is returned if the operation succeeded. SCI_FAILURE_INVALID_STATE
- * This value is returned if the attempt to change the user parameter failed,
- * because changing one of the parameters is not currently allowed.
- * SCI_FAILURE_INVALID_PARAMETER_VALUE This value is returned if the user
- * supplied an unsupported value for one of the OEM parameters.
- */
-enum sci_status scic_oem_parameters_set(
-	struct scic_sds_controller *controller,
-	union scic_oem_parameters *oem_parameters);
-
 int scic_oem_parameters_validate(struct scic_sds_oem_params *oem);
 
 /**
diff --git a/drivers/scsi/isci/core/scic_controller.h b/drivers/scsi/isci/core/scic_controller.h
deleted file mode 100644
index bd08f306ed67..000000000000
--- a/drivers/scsi/isci/core/scic_controller.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * This file is provided under a dual BSD/GPLv2 license.  When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
- * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- * The full GNU General Public License is included in this distribution
- * in the file called LICENSE.GPL.
- *
- * BSD LICENSE
- *
- * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *   * Neither the name of Intel Corporation nor the names of its
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _SCIC_CONTROLLER_H_
-#define _SCIC_CONTROLLER_H_
-
-#include "scic_config_parameters.h"
-
-struct scic_sds_request;
-struct scic_sds_phy;
-struct scic_sds_port;
-struct scic_sds_remote_device;
-
-enum sci_status scic_controller_construct(struct scic_sds_controller *c,
-					  void __iomem *scu_base,
-					  void __iomem *smu_base);
-
-void scic_controller_enable_interrupts(
-	struct scic_sds_controller *controller);
-
-void scic_controller_disable_interrupts(
-	struct scic_sds_controller *controller);
-
-enum sci_status scic_controller_initialize(
-	struct scic_sds_controller *controller);
-
-u32 scic_controller_get_suggested_start_timeout(
-	struct scic_sds_controller *controller);
-
-enum sci_status scic_controller_start(
-	struct scic_sds_controller *controller,
-	u32 timeout);
-
-enum sci_status scic_controller_stop(
-	struct scic_sds_controller *controller,
-	u32 timeout);
-
-enum sci_status scic_controller_reset(
-	struct scic_sds_controller *controller);
-
-enum sci_status scic_controller_start_io(
-	struct scic_sds_controller *controller,
-	struct scic_sds_remote_device *remote_device,
-	struct scic_sds_request *io_request,
-	u16 io_tag);
-
-enum sci_task_status scic_controller_start_task(
-	struct scic_sds_controller *controller,
-	struct scic_sds_remote_device *remote_device,
-	struct scic_sds_request *task_request,
-	u16 io_tag);
-
-enum sci_status scic_controller_terminate_request(
-	struct scic_sds_controller *controller,
-	struct scic_sds_remote_device *remote_device,
-	struct scic_sds_request *request);
-
-enum sci_status scic_controller_complete_io(
-	struct scic_sds_controller *controller,
-	struct scic_sds_remote_device *remote_device,
-	struct scic_sds_request *io_request);
-
-enum sci_status scic_controller_get_phy_handle(
-	struct scic_sds_controller *controller,
-	u8 phy_index,
-	struct scic_sds_phy **phy_handle);
-
-u16 scic_controller_allocate_io_tag(
-	struct scic_sds_controller *controller);
-
-enum sci_status scic_controller_free_io_tag(
-	struct scic_sds_controller *controller,
-	u16 io_tag);
-
-struct device;
-struct scic_sds_controller *scic_controller_alloc(struct device *dev);
-int scic_controller_mem_init(struct scic_sds_controller *scic);
-#endif  /* _SCIC_CONTROLLER_H_ */
diff --git a/drivers/scsi/isci/core/scic_sds_controller.c b/drivers/scsi/isci/core/scic_sds_controller.c
deleted file mode 100644
index e77265b9b9ec..000000000000
--- a/drivers/scsi/isci/core/scic_sds_controller.c
+++ /dev/null
@@ -1,2973 +0,0 @@
-/*
- * This file is provided under a dual BSD/GPLv2 license.  When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
- * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- * The full GNU General Public License is included in this distribution
- * in the file called LICENSE.GPL.
- *
- * BSD LICENSE
- *
- * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *   * Neither the name of Intel Corporation nor the names of its
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <linux/device.h>
-#include <scsi/sas.h>
-#include "scic_controller.h"
-#include "scic_phy.h"
-#include "scic_port.h"
-#include "scic_sds_controller.h"
-#include "scu_registers.h"
-#include "scic_sds_phy.h"
-#include "scic_sds_port_configuration_agent.h"
-#include "scic_sds_port.h"
-#include "remote_device.h"
-#include "scic_sds_request.h"
-#include "sci_environment.h"
-#include "sci_util.h"
-#include "scu_completion_codes.h"
-#include "scu_event_codes.h"
-#include "scu_remote_node_context.h"
-#include "scu_task_context.h"
-#include "scu_unsolicited_frame.h"
-#include "timers.h"
-
-#define SCU_CONTEXT_RAM_INIT_STALL_TIME      200
-
-/**
- * smu_dcc_get_max_ports() -
- *
- * This macro returns the maximum number of logical ports supported by the
- * hardware. The caller passes in the value read from the device context
- * capacity register and this macro will mash and shift the value appropriately.
- */
-#define smu_dcc_get_max_ports(dcc_value) \
-	(\
-		(((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
-		 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \
-	)
-
-/**
- * smu_dcc_get_max_task_context() -
- *
- * This macro returns the maximum number of task contexts supported by the
- * hardware. The caller passes in the value read from the device context
- * capacity register and this macro will mash and shift the value appropriately.
- */
-#define smu_dcc_get_max_task_context(dcc_value)	\
-	(\
-		(((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
-		 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \
-	)
-
-/**
- * smu_dcc_get_max_remote_node_context() -
- *
- * This macro returns the maximum number of remote node contexts supported by
- * the hardware. The caller passes in the value read from the device context
- * capacity register and this macro will mash and shift the value appropriately.
- */
-#define smu_dcc_get_max_remote_node_context(dcc_value) \
-	(\
-		(((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
-		 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \
-	)
-
-
-static void scic_sds_controller_power_control_timer_handler(
-	void *controller);
-#define SCIC_SDS_CONTROLLER_MIN_TIMER_COUNT  3
-#define SCIC_SDS_CONTROLLER_MAX_TIMER_COUNT  3
-
-/**
- *
- *
- * The number of milliseconds to wait for a phy to start.
- */
-#define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT      100
-
-/**
- *
- *
- * The number of milliseconds to wait while a given phy is consuming power
- * before allowing another set of phys to consume power. Ultimately, this will
- * be specified by OEM parameter.
- */
-#define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500
-
-/**
- * COMPLETION_QUEUE_CYCLE_BIT() -
- *
- * This macro will return the cycle bit of the completion queue entry
- */
-#define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000)
-
-/**
- * NORMALIZE_GET_POINTER() -
- *
- * This macro will normalize the completion queue get pointer so its value can
- * be used as an index into an array
- */
-#define NORMALIZE_GET_POINTER(x) \
-	((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK)
-
-/**
- * NORMALIZE_PUT_POINTER() -
- *
- * This macro will normalize the completion queue put pointer so its value can
- * be used as an array inde
- */
-#define NORMALIZE_PUT_POINTER(x) \
-	((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK)
-
-
-/**
- * NORMALIZE_GET_POINTER_CYCLE_BIT() -
- *
- * This macro will normalize the completion queue cycle pointer so it matches
- * the completion queue cycle bit
- */
-#define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \
-	((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
-
-/**
- * NORMALIZE_EVENT_POINTER() -
- *
- * This macro will normalize the completion queue event entry so its value can
- * be used as an index.
- */
-#define NORMALIZE_EVENT_POINTER(x) \
-	(\
-		((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \
-		>> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT	\
-	)
-
-/**
- * INCREMENT_COMPLETION_QUEUE_GET() -
- *
- * This macro will increment the controllers completion queue index value and
- * possibly toggle the cycle bit if the completion queue index wraps back to 0.
- */
-#define INCREMENT_COMPLETION_QUEUE_GET(controller, index, cycle) \
-	INCREMENT_QUEUE_GET(\
-		(index), \
-		(cycle), \
-		(controller)->completion_queue_entries,	\
-		SMU_CQGR_CYCLE_BIT \
-		)
-
-/**
- * INCREMENT_EVENT_QUEUE_GET() -
- *
- * This macro will increment the controllers event queue index value and
- * possibly toggle the event cycle bit if the event queue index wraps back to 0.
- */
-#define INCREMENT_EVENT_QUEUE_GET(controller, index, cycle) \
-	INCREMENT_QUEUE_GET(\
-		(index), \
-		(cycle), \
-		(controller)->completion_event_entries,	\
-		SMU_CQGR_EVENT_CYCLE_BIT \
-		)
-
-static void scic_sds_controller_initialize_power_control(struct scic_sds_controller *scic)
-{
-	struct isci_host *ihost = scic_to_ihost(scic);
-	scic->power_control.timer = isci_timer_create(ihost,
-						      scic,
-					scic_sds_controller_power_control_timer_handler);
-
-	memset(scic->power_control.requesters, 0,
-	       sizeof(scic->power_control.requesters));
-
-	scic->power_control.phys_waiting = 0;
-	scic->power_control.phys_granted_power = 0;
-}
-
-int scic_controller_mem_init(struct scic_sds_controller *scic)
-{
-	struct device *dev = scic_to_dev(scic);
-	dma_addr_t dma_handle;
-	enum sci_status result;
-
-	scic->completion_queue = dmam_alloc_coherent(dev,
-			scic->completion_queue_entries * sizeof(u32),
-			&dma_handle, GFP_KERNEL);
-	if (!scic->completion_queue)
-		return -ENOMEM;
-
-	writel(lower_32_bits(dma_handle),
-		&scic->smu_registers->completion_queue_lower);
-	writel(upper_32_bits(dma_handle),
-		&scic->smu_registers->completion_queue_upper);
-
-	scic->remote_node_context_table = dmam_alloc_coherent(dev,
-			scic->remote_node_entries *
-				sizeof(union scu_remote_node_context),
-			&dma_handle, GFP_KERNEL);
-	if (!scic->remote_node_context_table)
-		return -ENOMEM;
-
-	writel(lower_32_bits(dma_handle),
-		&scic->smu_registers->remote_node_context_lower);
-	writel(upper_32_bits(dma_handle),
-		&scic->smu_registers->remote_node_context_upper);
-
-	scic->task_context_table = dmam_alloc_coherent(dev,
-			scic->task_context_entries *
-				sizeof(struct scu_task_context),
-			&dma_handle, GFP_KERNEL);
-	if (!scic->task_context_table)
-		return -ENOMEM;
-
-	writel(lower_32_bits(dma_handle),
-		&scic->smu_registers->host_task_table_lower);
-	writel(upper_32_bits(dma_handle),
-		&scic->smu_registers->host_task_table_upper);
-
-	result = scic_sds_unsolicited_frame_control_construct(scic);
-	if (result)
-		return result;
-
-	/*
-	 * Inform the silicon as to the location of the UF headers and
-	 * address table.
-	 */
-	writel(lower_32_bits(scic->uf_control.headers.physical_address),
-		&scic->scu_registers->sdma.uf_header_base_address_lower);
-	writel(upper_32_bits(scic->uf_control.headers.physical_address),
-		&scic->scu_registers->sdma.uf_header_base_address_upper);
-
-	writel(lower_32_bits(scic->uf_control.address_table.physical_address),
-		&scic->scu_registers->sdma.uf_address_table_lower);
-	writel(upper_32_bits(scic->uf_control.address_table.physical_address),
-		&scic->scu_registers->sdma.uf_address_table_upper);
-
-	return 0;
-}
-
-/**
- * This method initializes the task context data for the controller.
- * @scic:
- *
- */
-static void
-scic_sds_controller_assign_task_entries(struct scic_sds_controller *controller)
-{
-	u32 task_assignment;
-
-	/*
-	 * Assign all the TCs to function 0
-	 * TODO: Do we actually need to read this register to write it back?
-	 */
-
-	task_assignment =
-		readl(&controller->smu_registers->task_context_assignment[0]);
-
-	task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) |
-		(SMU_TCA_GEN_VAL(ENDING,  controller->task_context_entries - 1)) |
-		(SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE));
-
-	writel(task_assignment,
-		&controller->smu_registers->task_context_assignment[0]);
-
-}
-
-/**
- * This method initializes the hardware completion queue.
- *
- *
- */
-static void scic_sds_controller_initialize_completion_queue(
-	struct scic_sds_controller *scic)
-{
-	u32 index;
-	u32 completion_queue_control_value;
-	u32 completion_queue_get_value;
-	u32 completion_queue_put_value;
-
-	scic->completion_queue_get = 0;
-
-	completion_queue_control_value = (
-		SMU_CQC_QUEUE_LIMIT_SET(scic->completion_queue_entries - 1)
-		| SMU_CQC_EVENT_LIMIT_SET(scic->completion_event_entries - 1)
-		);
-
-	writel(completion_queue_control_value,
-	       &scic->smu_registers->completion_queue_control);
-
-
-	/* Set the completion queue get pointer and enable the queue */
-	completion_queue_get_value = (
-		(SMU_CQGR_GEN_VAL(POINTER, 0))
-		| (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0))
-		| (SMU_CQGR_GEN_BIT(ENABLE))
-		| (SMU_CQGR_GEN_BIT(EVENT_ENABLE))
-		);
-
-	writel(completion_queue_get_value,
-	       &scic->smu_registers->completion_queue_get);
-
-	/* Set the completion queue put pointer */
-	completion_queue_put_value = (
-		(SMU_CQPR_GEN_VAL(POINTER, 0))
-		| (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0))
-		);
-
-	writel(completion_queue_put_value,
-	       &scic->smu_registers->completion_queue_put);
-
-	/* Initialize the cycle bit of the completion queue entries */
-	for (index = 0; index < scic->completion_queue_entries; index++) {
-		/*
-		 * If get.cycle_bit != completion_queue.cycle_bit
-		 * its not a valid completion queue entry
-		 * so at system start all entries are invalid */
-		scic->completion_queue[index] = 0x80000000;
-	}
-}
-
-/**
- * This method initializes the hardware unsolicited frame queue.
- *
- *
- */
-static void scic_sds_controller_initialize_unsolicited_frame_queue(
-	struct scic_sds_controller *scic)
-{
-	u32 frame_queue_control_value;
-	u32 frame_queue_get_value;
-	u32 frame_queue_put_value;
-
-	/* Write the queue size */
-	frame_queue_control_value =
-		SCU_UFQC_GEN_VAL(QUEUE_SIZE,
-				 scic->uf_control.address_table.count);
-
-	writel(frame_queue_control_value,
-	       &scic->scu_registers->sdma.unsolicited_frame_queue_control);
-
-	/* Setup the get pointer for the unsolicited frame queue */
-	frame_queue_get_value = (
-		SCU_UFQGP_GEN_VAL(POINTER, 0)
-		|  SCU_UFQGP_GEN_BIT(ENABLE_BIT)
-		);
-
-	writel(frame_queue_get_value,
-	       &scic->scu_registers->sdma.unsolicited_frame_get_pointer);
-	/* Setup the put pointer for the unsolicited frame queue */
-	frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0);
-	writel(frame_queue_put_value,
-	       &scic->scu_registers->sdma.unsolicited_frame_put_pointer);
-}
-
-/**
- * This method enables the hardware port task scheduler.
- *
- *
- */
-static void scic_sds_controller_enable_port_task_scheduler(
-	struct scic_sds_controller *scic)
-{
-	u32 port_task_scheduler_value;
-
-	port_task_scheduler_value =
-		readl(&scic->scu_registers->peg0.ptsg.control);
-	port_task_scheduler_value |=
-		(SCU_PTSGCR_GEN_BIT(ETM_ENABLE) |
-		 SCU_PTSGCR_GEN_BIT(PTSG_ENABLE));
-	writel(port_task_scheduler_value,
-	       &scic->scu_registers->peg0.ptsg.control);
-}
-
-/**
- *
- *
- * This macro is used to delay between writes to the AFE registers during AFE
- * initialization.
- */
-#define AFE_REGISTER_WRITE_DELAY 10
-
-/* Initialize the AFE for this phy index. We need to read the AFE setup from
- * the OEM parameters none
- */
-static void scic_sds_controller_afe_initialization(struct scic_sds_controller *scic)
-{
-	const struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1;
-	u32 afe_status;
-	u32 phy_id;
-
-	/* Clear DFX Status registers */
-	writel(0x0081000f, &scic->scu_registers->afe.afe_dfx_master_control0);
-	udelay(AFE_REGISTER_WRITE_DELAY);
-
-	if (is_b0()) {
-		/* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
-		 * Timer, PM Stagger Timer */
-		writel(0x0007BFFF, &scic->scu_registers->afe.afe_pmsn_master_control2);
-		udelay(AFE_REGISTER_WRITE_DELAY);
-	}
-
-	/* Configure bias currents to normal */
-	if (is_a0())
-		writel(0x00005500, &scic->scu_registers->afe.afe_bias_control);
-	else if (is_a2())
-		writel(0x00005A00, &scic->scu_registers->afe.afe_bias_control);
-	else if (is_b0())
-		writel(0x00005F00, &scic->scu_registers->afe.afe_bias_control);
-
-	udelay(AFE_REGISTER_WRITE_DELAY);
-
-	/* Enable PLL */
-	if (is_b0())
-		writel(0x80040A08, &scic->scu_registers->afe.afe_pll_control0);
-	else
-		writel(0x80040908, &scic->scu_registers->afe.afe_pll_control0);
-
-	udelay(AFE_REGISTER_WRITE_DELAY);
-
-	/* Wait for the PLL to lock */
-	do {
-		afe_status = readl(&scic->scu_registers->afe.afe_common_block_status);
-		udelay(AFE_REGISTER_WRITE_DELAY);
-	} while ((afe_status & 0x00001000) == 0);
-
-	if (is_a0() || is_a2()) {
-		/* Shorten SAS SNW lock time (RxLock timer value from 76 us to 50 us) */
-		writel(0x7bcc96ad, &scic->scu_registers->afe.afe_pmsn_master_control0);
-		udelay(AFE_REGISTER_WRITE_DELAY);
-	}
-
-	for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
-		const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
-
-		if (is_b0()) {
-			 /* Configure transmitter SSC parameters */
-			writel(0x00030000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control);
-			udelay(AFE_REGISTER_WRITE_DELAY);
-		} else {
-			/*
-			 * All defaults, except the Receive Word Alignament/Comma Detect
-			 * Enable....(0xe800) */
-			writel(0x00004512, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
-			udelay(AFE_REGISTER_WRITE_DELAY);
-
-			writel(0x0050100F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control1);
-			udelay(AFE_REGISTER_WRITE_DELAY);
-		}
-
-		/*
-		 * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
-		 * & increase TX int & ext bias 20%....(0xe85c) */
-		if (is_a0())
-			writel(0x000003D4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
-		else if (is_a2())
-			writel(0x000003F0, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
-		else {
-			 /* Power down TX and RX (PWRDNTX and PWRDNRX) */
-			writel(0x000003d7, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
-			udelay(AFE_REGISTER_WRITE_DELAY);
-
-			/*
-			 * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
-			 * & increase TX int & ext bias 20%....(0xe85c) */
-			writel(0x000003d4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
-		}
-		udelay(AFE_REGISTER_WRITE_DELAY);
-
-		if (is_a0() || is_a2()) {
-			/* Enable TX equalization (0xe824) */
-			writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
-			udelay(AFE_REGISTER_WRITE_DELAY);
-		}
-
-		/*
-		 * RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0, TPD=0x0(TX Power On),
-		 * RDD=0x0(RX Detect Enabled) ....(0xe800) */
-		writel(0x00004100, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
-		udelay(AFE_REGISTER_WRITE_DELAY);
-
-		/* Leave DFE/FFE on */
-		if (is_a0())
-			writel(0x3F09983F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
-		else if (is_a2())
-			writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
-		else {
-			writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
-			udelay(AFE_REGISTER_WRITE_DELAY);
-			/* Enable TX equalization (0xe824) */
-			writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
-		}
-		udelay(AFE_REGISTER_WRITE_DELAY);
-
-		writel(oem_phy->afe_tx_amp_control0,
-			&scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control0);
-		udelay(AFE_REGISTER_WRITE_DELAY);
-
-		writel(oem_phy->afe_tx_amp_control1,
-			&scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control1);
-		udelay(AFE_REGISTER_WRITE_DELAY);
-
-		writel(oem_phy->afe_tx_amp_control2,
-			&scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control2);
-		udelay(AFE_REGISTER_WRITE_DELAY);
-
-		writel(oem_phy->afe_tx_amp_control3,
-			&scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control3);
-		udelay(AFE_REGISTER_WRITE_DELAY);
-	}
-
-	/* Transfer control to the PEs */
-	writel(0x00010f00, &scic->scu_registers->afe.afe_dfx_master_control0);
-	udelay(AFE_REGISTER_WRITE_DELAY);
-}
-
-/*
- * ****************************************************************************-
- * * SCIC SDS Controller Internal Start/Stop Routines
- * ****************************************************************************- */
-
-
-/**
- * This method will attempt to transition into the ready state for the
- *    controller and indicate that the controller start operation h