diff options
| author | Jayesh Choudhary <j-choudhary@ti.com> | 2022-11-01 01:36:33 +0530 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2022-11-16 21:11:12 -0600 |
| commit | 027b85ca972f321629af85793bb49d45382e9006 (patch) | |
| tree | b4af9ab920d951062d71705e6d80ffa5344c340a /arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | |
| parent | c1e56c8250a234d9bcd9e2f060da229688dfd9eb (diff) | |
| download | linux-027b85ca972f321629af85793bb49d45382e9006.tar.gz linux-027b85ca972f321629af85793bb49d45382e9006.tar.bz2 linux-027b85ca972f321629af85793bb49d45382e9006.zip | |
arm64: dts: ti: k3-j721s2-main: Enable crypto accelerator
Add the node for SA2UL for supporting hardware crypto algorithms,
including SHA1, SHA256, SHA512, AES, 3DES and AEAD suites.
Add rng node for hardware random number generator.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Acked-by: Matt Ranostay <mranostay@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20221031200633.26997-1-j-choudhary@ti.com
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 7ccf8a761fc9..8915132efcc1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -72,6 +72,25 @@ pinctrl-single,function-mask = <0xffffffff>; }; + main_crypto: crypto@4e00000 { + compatible = "ti,j721e-sa2ul"; + reg = <0x00 0x04e00000 0x00 0x1200>; + power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; + + dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, + <&main_udmap 0x4a41>; + dma-names = "tx", "rx1", "rx2"; + + rng: rng@4e10000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x00 0x04e10000 0x00 0x7d>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x200>; |