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| author | Vaishnav Achath <vaishnav.a@ti.com> | 2023-03-21 13:58:26 +0530 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2023-03-30 12:08:19 -0500 |
| commit | 04d7cb647b8527398e292c0b6960980de5359d09 (patch) | |
| tree | 991217cbf6746373d58d002f3e181acd3ea4a6b2 /arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | |
| parent | 8f6c475f4ca7a82d5203e20d33a6bb522902b44c (diff) | |
| download | linux-04d7cb647b8527398e292c0b6960980de5359d09.tar.gz linux-04d7cb647b8527398e292c0b6960980de5359d09.tar.bz2 linux-04d7cb647b8527398e292c0b6960980de5359d09.zip | |
arm64: dts: ti: k3-j721s2: Add MCSPI nodes
J721S2 has 8 MCSPI instances in the main domain and 3 instances
in the MCU domain. Add the DT nodes for all the 11 instances and
keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2
by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out
externally.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Keerthy <j-keerthy@ti.com>
Link: https://lore.kernel.org/r/20230321082827.14274-4-vaishnav.a@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 5da5f0cf7009..a353705a7463 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -203,6 +203,39 @@ status = "disabled"; }; + mcu_spi0: spi@40300000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040300000 0x00 0x400>; + interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 347 0>; + status = "disabled"; + }; + + mcu_spi1: spi@40310000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040310000 0x00 0x400>; + interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 348 0>; + status = "disabled"; + }; + + mcu_spi2: spi@40320000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040320000 0x00 0x400>; + interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 349 0>; + status = "disabled"; + }; + mcu_navss: bus@28380000{ compatible = "simple-mfd"; #address-cells = <2>; |