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authorMauro Carvalho Chehab <mchehab@s-opensource.com>2016-07-08 18:14:03 -0300
committerMauro Carvalho Chehab <mchehab@s-opensource.com>2016-07-08 18:14:03 -0300
commitfb810cb5eda8c47e3afbb45ea6b9676841d29e8d (patch)
tree618af9a957c6744e59d0183619a2e6cbbf685233 /arch/arm64/mm/context.c
parent241d9bb3427e1d074daa864a65730412b9a47a39 (diff)
parenta99cde438de0c4c0cecc1d1af1a55a75b10bfdef (diff)
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Merge tag 'v4.7-rc6' into patchwork
Linux 4.7-rc6 * tag 'v4.7-rc6': (1245 commits) Linux 4.7-rc6 ovl: warn instead of error if d_type is not supported MIPS: Fix possible corruption of cache mode by mprotect. locks: use file_inode() usb: dwc3: st: Use explicit reset_control_get_exclusive() API phy: phy-stih407-usb: Use explicit reset_control_get_exclusive() API phy: miphy28lp: Inform the reset framework that our reset line may be shared namespace: update event counter when umounting a deleted dentry 9p: use file_dentry() lockd: unregister notifier blocks if the service fails to come up completely ACPI,PCI,IRQ: correct operator precedence fuse: serialize dirops by default drm/i915: Fix missing unlock on error in i915_ppgtt_info() powerpc: Initialise pci_io_base as early as possible mfd: da9053: Fix compiler warning message for uninitialised variable mfd: max77620: Fix FPS switch statements phy: phy-stih407-usb: Inform the reset framework that our reset line may be shared usb: dwc3: st: Inform the reset framework that our reset line may be shared usb: host: ehci-st: Inform the reset framework that our reset line may be shared usb: host: ohci-st: Inform the reset framework that our reset line may be shared ...
Diffstat (limited to 'arch/arm64/mm/context.c')
-rw-r--r--arch/arm64/mm/context.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index b7b397802088..efcf1f7ef1e4 100644
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -179,7 +179,7 @@ static u64 new_context(struct mm_struct *mm, unsigned int cpu)
&asid_generation);
flush_context(cpu);
- /* We have at least 1 ASID per CPU, so this will always succeed */
+ /* We have more ASIDs than CPUs, so this will always succeed */
asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);
set_asid:
@@ -227,8 +227,11 @@ switch_mm_fastpath:
static int asids_init(void)
{
asid_bits = get_cpu_asid_bits();
- /* If we end up with more CPUs than ASIDs, expect things to crash */
- WARN_ON(NUM_USER_ASIDS < num_possible_cpus());
+ /*
+ * Expect allocation after rollover to fail if we don't have at least
+ * one more ASID than CPUs. ASID #0 is reserved for init_mm.
+ */
+ WARN_ON(NUM_USER_ASIDS - 1 <= num_possible_cpus());
atomic64_set(&asid_generation, ASID_FIRST_VERSION);
asid_map = kzalloc(BITS_TO_LONGS(NUM_USER_ASIDS) * sizeof(*asid_map),
GFP_KERNEL);