diff options
| author | Ingo Molnar <mingo@kernel.org> | 2012-09-19 17:32:12 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2012-09-19 17:32:12 +0200 |
| commit | 81a15f2ee56fe725ce68e3cdad982117e261d47d (patch) | |
| tree | 930188dd285b2c2b8c0625849d24bf68ed1f0ca0 /arch/c6x/include/asm/cache.h | |
| parent | 0570a365a6b8ccbfe7baa459de2b7396ddf2de90 (diff) | |
| parent | 5698bd757d55b1bb87edd1a9744ab09c142abfc2 (diff) | |
| download | linux-81a15f2ee56fe725ce68e3cdad982117e261d47d.tar.gz linux-81a15f2ee56fe725ce68e3cdad982117e261d47d.tar.bz2 linux-81a15f2ee56fe725ce68e3cdad982117e261d47d.zip | |
Merge tag 'v3.6-rc6' into x86/cleanups
Merge Linux v3.6-rc6 before applying more cleanups.
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/c6x/include/asm/cache.h')
| -rw-r--r-- | arch/c6x/include/asm/cache.h | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/c6x/include/asm/cache.h b/arch/c6x/include/asm/cache.h index 6d521d96d941..09c5a0f5f4d1 100644 --- a/arch/c6x/include/asm/cache.h +++ b/arch/c6x/include/asm/cache.h @@ -1,7 +1,7 @@ /* * Port on Texas Instruments TMS320C6x architecture * - * Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated + * Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com) * * This program is free software; you can redistribute it and/or modify @@ -16,9 +16,14 @@ /* * Cache line size */ -#define L1D_CACHE_BYTES 64 -#define L1P_CACHE_BYTES 32 -#define L2_CACHE_BYTES 128 +#define L1D_CACHE_SHIFT 6 +#define L1D_CACHE_BYTES (1 << L1D_CACHE_SHIFT) + +#define L1P_CACHE_SHIFT 5 +#define L1P_CACHE_BYTES (1 << L1P_CACHE_SHIFT) + +#define L2_CACHE_SHIFT 7 +#define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) /* * L2 used as cache @@ -29,7 +34,8 @@ * For practical reasons the L1_CACHE_BYTES defines should not be smaller than * the L2 line size */ -#define L1_CACHE_BYTES L2_CACHE_BYTES +#define L1_CACHE_SHIFT L2_CACHE_SHIFT +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) #define L2_CACHE_ALIGN_LOW(x) \ (((x) & ~(L2_CACHE_BYTES - 1))) |