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| author | Rob Clark <robdclark@chromium.org> | 2021-12-06 09:13:49 -0800 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2021-12-06 09:14:28 -0800 |
| commit | 83b965d118cbab1dbdfffdff8cabc8c1cfd183c6 (patch) | |
| tree | f46a8f6d854b05a47311125f6fd6b6081e79557a /arch/hexagon/kernel/time.c | |
| parent | fee32807633395e666f0951d6b7b6546e9b76c3d (diff) | |
| parent | c305ae99dfd4d0fe70c7fdf13ef5f7650a804ea7 (diff) | |
| download | linux-83b965d118cbab1dbdfffdff8cabc8c1cfd183c6.tar.gz linux-83b965d118cbab1dbdfffdff8cabc8c1cfd183c6.tar.bz2 linux-83b965d118cbab1dbdfffdff8cabc8c1cfd183c6.zip | |
Merge remote-tracking branch 'drm/drm-next' into msm-next-staging
Backmerge drm-next to pull in:
8f59ee9a570c ("drm/msm/dsi: Adjust probe order")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'arch/hexagon/kernel/time.c')
| -rw-r--r-- | arch/hexagon/kernel/time.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/hexagon/kernel/time.c b/arch/hexagon/kernel/time.c index feffe527ac92..febc95714d75 100644 --- a/arch/hexagon/kernel/time.c +++ b/arch/hexagon/kernel/time.c @@ -17,9 +17,10 @@ #include <linux/of_irq.h> #include <linux/module.h> -#include <asm/timer-regs.h> #include <asm/hexagon_vm.h> +#define TIMER_ENABLE BIT(0) + /* * For the clocksource we need: * pcycle frequency (600MHz) @@ -33,6 +34,13 @@ cycles_t pcycle_freq_mhz; cycles_t thread_freq_mhz; cycles_t sleep_clk_freq; +/* + * 8x50 HDD Specs 5-8. Simulator co-sim not fixed until + * release 1.1, and then it's "adjustable" and probably not defaulted. + */ +#define RTOS_TIMER_INT 3 +#define RTOS_TIMER_REGS_ADDR 0xAB000000UL + static struct resource rtos_timer_resources[] = { { .start = RTOS_TIMER_REGS_ADDR, @@ -80,7 +88,7 @@ static int set_next_event(unsigned long delta, struct clock_event_device *evt) iowrite32(0, &rtos_timer->clear); iowrite32(delta, &rtos_timer->match); - iowrite32(1 << TIMER_ENABLE, &rtos_timer->enable); + iowrite32(TIMER_ENABLE, &rtos_timer->enable); return 0; } |