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| author | Ingo Molnar <mingo@kernel.org> | 2021-10-16 15:17:46 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2021-10-16 15:17:46 +0200 |
| commit | 082f20b21de20285da2cbfc1be29656f0714c1b8 (patch) | |
| tree | 6170af99f1491fe256351b9cf92725dbda79c153 /arch/mips/include/asm/mips-cps.h | |
| parent | 724fc0248d450224b19ef5b5ee41e392348f6704 (diff) | |
| parent | b2381acd3fd9bacd2c63f53b2c610c89959b31cc (diff) | |
| download | linux-082f20b21de20285da2cbfc1be29656f0714c1b8.tar.gz linux-082f20b21de20285da2cbfc1be29656f0714c1b8.tar.bz2 linux-082f20b21de20285da2cbfc1be29656f0714c1b8.zip | |
Merge branch 'x86/urgent' into x86/fpu, to resolve a conflict
Resolve the conflict between these commits:
x86/fpu: 1193f408cd51 ("x86/fpu/signal: Change return type of __fpu_restore_sig() to boolean")
x86/urgent: d298b03506d3 ("x86/fpu: Restore the masking out of reserved MXCSR bits")
b2381acd3fd9 ("x86/fpu: Mask out the invalid MXCSR bits properly")
Conflicts:
arch/x86/kernel/fpu/signal.c
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/mips/include/asm/mips-cps.h')
| -rw-r--r-- | arch/mips/include/asm/mips-cps.h | 23 |
1 files changed, 1 insertions, 22 deletions
diff --git a/arch/mips/include/asm/mips-cps.h b/arch/mips/include/asm/mips-cps.h index 35fb8ee6dd33..fd43d876892e 100644 --- a/arch/mips/include/asm/mips-cps.h +++ b/arch/mips/include/asm/mips-cps.h @@ -10,8 +10,6 @@ #include <linux/io.h> #include <linux/types.h> -#include <asm/mips-boards/launch.h> - extern unsigned long __cps_access_bad_size(void) __compiletime_error("Bad size for CPS accessor"); @@ -167,30 +165,11 @@ static inline uint64_t mips_cps_cluster_config(unsigned int cluster) */ static inline unsigned int mips_cps_numcores(unsigned int cluster) { - unsigned int ncores; - if (!mips_cm_present()) return 0; /* Add one before masking to handle 0xff indicating no cores */ - ncores = (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES; - - if (IS_ENABLED(CONFIG_SOC_MT7621)) { - struct cpulaunch *launch; - - /* - * Ralink MT7621S SoC is single core, but the GCR_CONFIG method - * always reports 2 cores. Check the second core's LAUNCH_FREADY - * flag to detect if the second core is missing. This method - * only works before the core has been started. - */ - launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); - launch += 2; /* MT7621 has 2 VPEs per core */ - if (!(launch->flags & LAUNCH_FREADY)) - ncores = 1; - } - - return ncores; + return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES; } /** |