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| author | Evan Green <evan@rivosinc.com> | 2024-08-09 14:44:44 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-08-14 13:13:24 -0700 |
| commit | 1f5288874de776412041022607513ffac74ae1a6 (patch) | |
| tree | f3c3b563dfbbff5ca7c1986203aac924301dca47 /arch/riscv/include/uapi/asm/hwprobe.h | |
| parent | c42e2f076769c9c1bc5f3f0aa1c2032558e76647 (diff) | |
| download | linux-1f5288874de776412041022607513ffac74ae1a6.tar.gz linux-1f5288874de776412041022607513ffac74ae1a6.tar.bz2 linux-1f5288874de776412041022607513ffac74ae1a6.zip | |
RISC-V: hwprobe: Add SCALAR to misaligned perf defines
In preparation for misaligned vector performance hwprobe keys, rename
the hwprobe key values associated with misaligned scalar accesses to
include the term SCALAR. Leave the old defines in place to maintain
source compatibility.
This change is intended to be a functional no-op.
Signed-off-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Link: https://lore.kernel.org/r/20240809214444.3257596-3-evan@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/include/uapi/asm/hwprobe.h')
| -rw-r--r-- | arch/riscv/include/uapi/asm/hwprobe.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 635753084275..1e153cda57db 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -83,6 +83,11 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS 7 #define RISCV_HWPROBE_KEY_TIME_CSR_FREQ 8 #define RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF 9 +#define RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN 0 +#define RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED 1 +#define RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW 2 +#define RISCV_HWPROBE_MISALIGNED_SCALAR_FAST 3 +#define RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED 4 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ /* Flags */ |