arch: remove tile port

The Tile architecture port was added by Chris Metcalf in 2010, and
maintained until early 2018 when he orphaned it due to his departure
from Mellanox, and nobody else stepped up to maintain it. The product
line is still around in the form of the BlueField SoC, but no longer
uses the Tile architecture.

There are also still products for sale with Tile-GX SoCs, notably the
Mikrotik CCR router family. The products all use old (linux-3.3) kernels
with lots of patches and won't be upgraded by their manufacturers. There
have been efforts to port both OpenWRT and Debian to these, but both
projects have stalled and are very unlikely to be continued in the future.

Given that we are reasonably sure that nobody is still using the port
with an upstream kernel any more, it seems better to remove it now while
the port is in a good shape than to let it bitrot for a few years first.

Cc: Chris Metcalf <chris.d.metcalf@gmail.com>
Cc: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Link: http://www.mellanox.com/page/npu_multicore_overview
Link: https://jenkins.debian.net/view/rebootstrap/job/rebootstrap_tilegx_gcc7/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

29 files changed, 0 insertions, 3313 deletions

diff --git a/arch/tile/lib/Makefile b/arch/tile/lib/Makefile
deleted file mode 100644
index 815a1fdeb2e4..000000000000
--- a/arch/tile/lib/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for TILE-specific library files..
-#
-
-lib-y = cacheflush.o checksum.o cpumask.o delay.o uaccess.o \
-	memmove.o memcpy_$(BITS).o memchr_$(BITS).o memset_$(BITS).o \
-	strchr_$(BITS).o strlen_$(BITS).o strnlen_$(BITS).o
-
-lib-$(CONFIG_TILEGX) += memcpy_user_64.o
-lib-$(CONFIG_TILEPRO) += atomic_32.o atomic_asm_32.o
-lib-$(CONFIG_SMP) += spinlock_$(BITS).o usercopy_$(BITS).o
-
-obj-$(CONFIG_MODULES) += exports.o
-
-# The finv_buffer_remote() and copy_{to,from}_user() routines can't
-# have -pg added, since they both rely on being leaf functions.
-CFLAGS_REMOVE_cacheflush.o = -pg
-CFLAGS_REMOVE_memcpy_user_64.o = -pg
diff --git a/arch/tile/lib/atomic_32.c b/arch/tile/lib/atomic_32.c
deleted file mode 100644
index f8128800dbf5..000000000000
--- a/arch/tile/lib/atomic_32.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- *   This program is free software; you can redistribute it and/or
- *   modify it under the terms of the GNU General Public License
- *   as published by the Free Software Foundation, version 2.
- *
- *   This program is distributed in the hope that it will be useful, but
- *   WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- *   NON INFRINGEMENT.  See the GNU General Public License for
- *   more details.
- */
-
-#include <linux/cache.h>
-#include <linux/delay.h>
-#include <linux/uaccess.h>
-#include <linux/module.h>
-#include <linux/mm.h>
-#include <linux/atomic.h>
-#include <arch/chip.h>
-
-/* This page is remapped on startup to be hash-for-home. */
-int atomic_locks[PAGE_SIZE / sizeof(int)] __page_aligned_bss;
-
-int *__atomic_hashed_lock(volatile void *v)
-{
-	/* NOTE: this code must match "sys_cmpxchg" in kernel/intvec_32.S */
-	/*
-	 * Use bits [3, 3 + ATOMIC_HASH_SHIFT) as the lock index.
-	 * Using mm works here because atomic_locks is page aligned.
-	 */
-	unsigned long ptr = __insn_mm((unsigned long)v >> 1,
-				      (unsigned long)atomic_locks,
-				      2, (ATOMIC_HASH_SHIFT + 2) - 1);
-	return (int *)ptr;
-}
-
-#ifdef CONFIG_SMP
-/* Return whether the passed pointer is a valid atomic lock pointer. */
-static int is_atomic_lock(int *p)
-{
-	return p >= &atomic_locks[0] && p < &atomic_locks[ATOMIC_HASH_SIZE];
-}
-
-void __atomic_fault_unlock(int *irqlock_word)
-{
-	BUG_ON(!is_atomic_lock(irqlock_word));
-	BUG_ON(*irqlock_word != 1);
-	*irqlock_word = 0;
-}
-
-#endif /* CONFIG_SMP */
-
-static inline int *__atomic_setup(volatile void *v)
-{
-	/* Issue a load to the target to bring it into cache. */
-	*(volatile int *)v;
-	return __atomic_hashed_lock(v);
-}
-
-int _atomic_xchg(int *v, int n)
-{
-	return __atomic32_xchg(v, __atomic_setup(v), n).val;
-}
-EXPORT_SYMBOL(_atomic_xchg);
-
-int _atomic_xchg_add(int *v, int i)
-{
-	return __atomic32_xchg_add(v, __atomic_setup(v), i).val;
-}
-EXPORT_SYMBOL(_atomic_xchg_add);
-
-int _atomic_xchg_add_unless(int *v, int a, int u)
-{
-	/*
-	 * Note: argument order is switched here since it is easier
-	 * to use the first argument consistently as the "old value"
-	 * in the assembly, as is done for _atomic_cmpxchg().
-	 */
-	return __atomic32_xchg_add_unless(v, __atomic_setup(v), u, a).val;
-}
-EXPORT_SYMBOL(_atomic_xchg_add_unless);
-
-int _atomic_cmpxchg(int *v, int o, int n)
-{
-	return __atomic32_cmpxchg(v, __atomic_setup(v), o, n).val;
-}
-EXPORT_SYMBOL(_atomic_cmpxchg);
-
-unsigned long _atomic_fetch_or(volatile unsigned long *p, unsigned long mask)
-{
-	return __atomic32_fetch_or((int *)p, __atomic_setup(p), mask).val;
-}
-EXPORT_SYMBOL(_atomic_fetch_or);
-
-unsigned long _atomic_fetch_and(volatile unsigned long *p, unsigned long mask)
-{
-	return __atomic32_fetch_and((int *)p, __atomic_setup(p), mask).val;
-}
-EXPORT_SYMBOL(_atomic_fetch_and);
-
-unsigned long _atomic_fetch_andn(volatile unsigned long *p, unsigned long mask)
-{
-	return __atomic32_fetch_andn((int *)p, __atomic_setup(p), mask).val;
-}
-EXPORT_SYMBOL(_atomic_fetch_andn);
-
-unsigned long _atomic_fetch_xor(volatile unsigned long *p, unsigned long mask)
-{
-	return __atomic32_fetch_xor((int *)p, __atomic_setup(p), mask).val;
-}
-EXPORT_SYMBOL(_atomic_fetch_xor);
-
-
-long long _atomic64_xchg(long long *v, long long n)
-{
-	return __atomic64_xchg(v, __atomic_setup(v), n);
-}
-EXPORT_SYMBOL(_atomic64_xchg);
-
-long long _atomic64_xchg_add(long long *v, long long i)
-{
-	return __atomic64_xchg_add(v, __atomic_setup(v), i);
-}
-EXPORT_SYMBOL(_atomic64_xchg_add);
-
-long long _atomic64_xchg_add_unless(long long *v, long long a, long long u)
-{
-	/*
-	 * Note: argument order is switched here since it is easier
-	 * to use the first argument consistently as the "old value"
-	 * in the assembly, as is done for _atomic_cmpxchg().
-	 */
-	return __atomic64_xchg_add_unless(v, __atomic_setup(v), u, a);
-}
-EXPORT_SYMBOL(_atomic64_xchg_add_unless);
-
-long long _atomic64_cmpxchg(long long *v, long long o, long long n)
-{
-	return __atomic64_cmpxchg(v, __atomic_setup(v), o, n);
-}
-EXPORT_SYMBOL(_atomic64_cmpxchg);
-
-long long _atomic64_fetch_and(long long *v, long long n)
-{
-	return __atomic64_fetch_and(v, __atomic_setup(v), n);
-}
-EXPORT_SYMBOL(_atomic64_fetch_and);
-
-long long _atomic64_fetch_or(long long *v, long long n)
-{
-	return __atomic64_fetch_or(v, __atomic_setup(v), n);
-}
-EXPORT_SYMBOL(_atomic64_fetch_or);
-
-long long _atomic64_fetch_xor(long long *v, long long n)
-{
-	return __atomic64_fetch_xor(v, __atomic_setup(v), n);
-}
-EXPORT_SYMBOL(_atomic64_fetch_xor);
-
-/*
- * If any of the atomic or futex routines hit a bad address (not in
- * the page tables at kernel PL) this routine is called.  The futex
- * routines are never used on kernel space, and the normal atomics and
- * bitops are never used on user space.  So a fault on kernel space
- * must be fatal, but a fault on userspace is a futex fault and we
- * need to return -EFAULT.  Note that the context this routine is
- * invoked in is the context of the "_atomic_xxx()" routines called
- * by the functions in this file.
- */
-struct __get_user __atomic_bad_address(int __user *addr)
-{
-	if (unlikely(!access_ok(VERIFY_WRITE, addr, sizeof(int))))
-		panic("Bad address used for kernel atomic op: %p\n", addr);
-	return (struct __get_user) { .err = -EFAULT };
-}
-
-
-void __init __init_atomic_per_cpu(void)
-{
-	/* Validate power-of-two and "bigger than cpus" assumption */
-	BUILD_BUG_ON(ATOMIC_HASH_SIZE & (ATOMIC_HASH_SIZE-1));
-	BUG_ON(ATOMIC_HASH_SIZE < nr_cpu_ids);
-
-	/*
-	 * On TILEPro we prefer to use a single hash-for-home
-	 * page, since this means atomic operations are less
-	 * likely to encounter a TLB fault and thus should
-	 * in general perform faster.  You may wish to disable
-	 * this in situations where few hash-for-home tiles
-	 * are configured.
-	 */
-	BUG_ON((unsigned long)atomic_locks % PAGE_SIZE != 0);
-
-	/* The locks must all fit on one page. */
-	BUILD_BUG_ON(ATOMIC_HASH_SIZE * sizeof(int) > PAGE_SIZE);
-
-	/*
-	 * We use the page offset of the atomic value's address as
-	 * an index into atomic_locks, excluding the low 3 bits.
-	 * That should not produce more indices than ATOMIC_HASH_SIZE.
-	 */
-	BUILD_BUG_ON((PAGE_SIZE >> 3) > ATOMIC_HASH_SIZE);
-}
diff --git a/arch/tile/lib/atomic_asm_32.S b/arch/tile/lib/atomic_asm_32.S
deleted file mode 100644
index 94709ab41ed8..000000000000
--- a/arch/tile/lib/atomic_asm_32.S
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- *   This program is free software; you can redistribute it and/or
- *   modify it under the terms of the GNU General Public License
- *   as published by the Free Software Foundation, version 2.
- *
- *   This program is distributed in the hope that it will be useful, but
- *   WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- *   NON INFRINGEMENT.  See the GNU General Public License for
- *   more details.
- *
- * Support routines for atomic operations.  Each function takes:
- *
- * r0: address to manipulate
- * r1: pointer to atomic lock guarding this operation (for ATOMIC_LOCK_REG)
- * r2: new value to write, or for cmpxchg/add_unless, value to compare against
- * r3: (cmpxchg/xchg_add_unless) new value to write or add;
- *     (atomic64 ops) high word of value to write
- * r4/r5: (cmpxchg64/add_unless64) new value to write or add
- *
- * The 32-bit routines return a "struct __get_user" so that the futex code
- * has an opportunity to return -EFAULT to the user if needed.
- * The 64-bit routines just return a "long long" with the value,
- * since they are only used from kernel space and don't expect to fault.
- * Support for 16-bit ops is included in the framework but we don't provide any.
- *
- * Note that the caller is advised to issue a suitable L1 or L2
- * prefetch on the address being manipulated to avoid extra stalls.
- * In addition, the hot path is on two icache lines, and we start with
- * a jump to the second line to make sure they are both in cache so
- * that we never stall waiting on icache fill while holding the lock.
- * (This doesn't work out with most 64-bit ops, since they consume
- * too many bundles, so may take an extra i-cache stall.)
- *
- * These routines set the INTERRUPT_CRITICAL_SECTION bit, just
- * like sys_cmpxchg(), so that NMIs like PERF_COUNT will not interrupt
- * the code, just page faults.
- *
- * If the load or store faults in a way that can be directly fixed in
- * the do_page_fault_ics() handler (e.g. a vmalloc reference) we fix it
- * directly, return to the instruction that faulted, and retry it.
- *
- * If the load or store faults in a way that potentially requires us
- * to release the atomic lock, then retry (e.g. a migrating PTE), we
- * reset the PC in do_page_fault_ics() to the "tns" instruction so
- * that on return we will reacquire the lock and restart the op.  We
- * are somewhat overloading the exception_table_entry notion by doing
- * this, since those entries are not normally used for migrating PTEs.
- *
- * If the main page fault handler discovers a bad address, it will see
- * the PC pointing to the "tns" instruction (due to the earlier
- * exception_table_entry processing in do_page_fault_ics), and
- * re-reset the PC to the fault handler, atomic_bad_address(), which
- * effectively takes over from the atomic op and can either return a
- * bad "struct __get_user" (for user addresses) or can just panic (for
- * bad kernel addresses).
- *
- * Note that if the value we would store is the same as what we
- * loaded, we bypass the store.  Other platforms with true atomics can
- * make the guarantee that a non-atomic __clear_bit(), for example,
- * can safely race with an atomic test_and_set_bit(); this example is
- * from bit_spinlock.h in slub_lock() / slub_unlock().  We can't do
- * that on Tile since the "atomic" op is really just a
- * read/modify/write, and can race with the non-atomic
- * read/modify/write.  However, if we can short-circuit the write when
- * it is not needed, in the atomic case, we avoid the race.
- */
-
-#include <linux/linkage.h>
-#include <asm/atomic_32.h>
-#include <asm/page.h>
-#include <asm/processor.h>
-
-	.section .text.atomic,"ax"
-ENTRY(__start_atomic_asm_code)
-
-	.macro  atomic_op, name, bitwidth, body
-	.align  64
-STD_ENTRY_SECTION(__atomic\name, .text.atomic)
-	{
-	 movei  r24, 1
-	 j      4f		/* branch to second cache line */
-	}
-1:	{
-	 .ifc \bitwidth,16
-	 lh     r22, r0
-	 .else
-	 lw     r22, r0
-	 addi   r28, r0, 4
-	 .endif
-	}
-	.ifc \bitwidth,64
-	lw      r23, r28
-	.endif
-	\body /* set r24, and r25 if 64-bit */
-	{
-	 seq    r26, r22, r24
-	 seq    r27, r23, r25
-	}
-	.ifc \bitwidth,64
-	bbnst   r27, 2f
-	.endif
-	bbs     r26, 3f		/* skip write-back if it's the same value */
-2:	{
-	 .ifc \bitwidth,16
-	 sh     r0, r24
-	 .else
-	 sw     r0, r24
-	 .endif
-	}
-	.ifc \bitwidth,64
-	sw      r28, r25
-	.endif
-	mf
-3:	{
-	 move   r0, r22
-	 .ifc \bitwidth,64
-	 move   r1, r23
-	 .else
-	 move   r1, zero
-	 .endif
-	 sw     ATOMIC_LOCK_REG_NAME, zero
-	}
-	mtspr   INTERRUPT_CRITICAL_SECTION, zero
-	jrp     lr
-4:	{
-	 move   ATOMIC_LOCK_REG_NAME, r1
-	 mtspr  INTERRUPT_CRITICAL_SECTION, r24
-	}
-#ifndef CONFIG_SMP
-	j       1b		/* no atomic locks */
-#else
-	{
-	 tns    r21, ATOMIC_LOCK_REG_NAME
-	 moveli r23, 2048       /* maximum backoff time in cycles */
-	}
-	{
-	 bzt    r21, 1b		/* branch if lock acquired */
-	 moveli r25, 32         /* starting backoff time in cycles */
-	}
-5:	mtspr   INTERRUPT_CRITICAL_SECTION, zero
-	mfspr   r26, CYCLE_LOW  /* get start point for this backoff */
-6:	mfspr   r22, CYCLE_LOW  /* test to see if we've backed off enough */
-	sub     r22, r22, r26
-	slt     r22, r22, r25
-	bbst    r22, 6b
-	{
-	 mtspr  INTERRUPT_CRITICAL_SECTION, r24
-	 shli   r25, r25, 1     /* double the backoff; retry the tns */
-	}
-	{
-	 tns    r21, ATOMIC_LOCK_REG_NAME
-	 slt    r26, r23, r25   /* is the proposed backoff too big? */
-	}
-	{
-	 bzt    r21, 1b		/* branch if lock acquired */
-	 mvnz   r25, r26, r23
-	}
-	j       5b
-#endif
-	STD_ENDPROC(__atomic\name)
-	.ifc \bitwidth,32
-	.pushsection __ex_table,"a"
-	.align  4
-	.word   1b, __atomic\name
-	.word   2b, __atomic\name
-	.word   __atomic\name, __atomic_bad_address
-	.popsection
-	.endif
-	.endm
-
-
-/*
- * Use __atomic32 prefix to avoid collisions with GCC builtin __atomic functions.
- */
-
-atomic_op 32_cmpxchg, 32, "seq r26, r22, r2; { bbns r26, 3f; move r24, r3 }"
-atomic_op 32_xchg, 32, "move r24, r2"
-atomic_op 32_xchg_add, 32, "add r24, r22, r2"
-atomic_op 32_xchg_add_unless, 32, \
-	"sne r26, r22, r2; { bbns r26, 3f; add r24, r22, r3 }"
-atomic_op 32_fetch_or, 32, "or r24, r22, r2"
-atomic_op 32_fetch_and, 32, "and r24, r22, r2"
-atomic_op 32_fetch_andn, 32, "nor r2, r2, zero; and r24, r22, r2"
-atomic_op 32_fetch_xor, 32, "xor r24, r22, r2"
-
-atomic_op 64_cmpxchg, 64, "{ seq r26, r22, r2; seq r27, r23, r3 }; \
-	{ bbns r26, 3f; move r24, r4 }; { bbns r27, 3f; move r25, r5 }"
-atomic_op 64_xchg, 64, "{ move r24, r2; move r25, r3 }"
-atomic_op 64_xchg_add, 64, "{ add r24, r22, r2; add r25, r23, r3 }; \
-	slt_u r26, r24, r22; add r25, r25, r26"
-atomic_op 64_xchg_add_unless, 64, \
-	"{ sne r26, r22, r2; sne r27, r23, r3 }; \
-	{ bbns r26, 3f; add r24, r22, r4 }; \
-	{ bbns r27, 3f; add r25, r23, r5 }; \
-	slt_u r26, r24, r22; add r25, r25, r26"
-atomic_op 64_fetch_or, 64, "{ or r24, r22, r2; or r25, r23, r3 }"
-atomic_op 64_fetch_and, 64, "{ and r24, r22, r2; and r25, r23, r3 }"
-atomic_op 64_fetch_xor, 64, "{ xor r24, r22, r2; xor r25, r23, r3 }"
-
-	jrp     lr              /* happy backtracer */
-
-ENTRY(__end_atomic_asm_code)
diff --git a/arch/tile/lib/cacheflush.c b/arch/tile/lib/cacheflush.c
deleted file mode 100644
index c1ebc1065fc1..000000000000
--- a/arch/tile/lib/cacheflush.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- *   This program is free software; you can redistribute it and/or
- *   modify it under the terms of the GNU General Public License
- *   as published by the Free Software Foundation, version 2.
- *
- *   This program is distributed in the hope that it will be useful, but
- *   WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- *   NON INFRINGEMENT.  See the GNU General Public License for
- *   more details.
- */
-
-#include <linux/export.h>
-#include <asm/page.h>
-#include <asm/cacheflush.h>
-#include <arch/icache.h>
-#include <arch/spr_def.h>
-
-
-void __flush_icache_range(unsigned long start, unsigned long end)
-{
-	invalidate_icache((const void *)start, end - start, PAGE_SIZE);
-}
-
-
-/* Force a load instruction to issue. */
-static inline void force_load(char *p)
-{
-	*(volatile char *)p;
-}
-
-/*
- * Flush and invalidate a VA range that is homed remotely on a single
- * core (if "!hfh") or homed via hash-for-home (if "hfh"), waiting
- * until the memory controller holds the flushed values.
- */
-void __attribute__((optimize("omit-frame-pointer")))
-finv_buffer_remote(void *buffer, size_t size, int hfh)
-{
-	char *p, *base;
-	size_t step_size, load_count;
-
-	/*
-	 * On TILEPro the striping granularity is a fixed 8KB; on
-	 * TILE-Gx it is configurable, and we rely on the fact that
-	 * the hypervisor always configures maximum striping, so that
-	 * bits 9 and 10 of the PA are part of the stripe function, so
-	 * every 512 bytes we hit a striping boundary.
-	 *
-	 */
-#ifdef __tilegx__
-	const unsigned long STRIPE_WIDTH = 512;
-#else
-	const unsigned long STRIPE_WIDTH = 8192;
-#endif
-
-#ifdef __tilegx__
-	/*
-	 * On TILE-Gx, we must disable the dstream prefetcher before doing
-	 * a cache flush; otherwise, we could end up with data in the cache
-	 * that we don't want there.  Note that normally we'd do an mf
-	 * after the SPR write to disabling the prefetcher, but we do one
-	 * below, before any further loads, so there's no need to do it
-	 * here.
-	 */
-	uint_reg_t old_dstream_pf = __insn_mfspr(SPR_DSTREAM_PF);
-	__insn_mtspr(SPR_DSTREAM_PF, 0);
-#endif
-
-	/*
-	 * Flush and invalidate the buffer out of the local L1/L2
-	 * and request the home cache to flush and invalidate as well.
-	 */
-	__finv_buffer(buffer, size);
-
-	/*
-	 * Wait for the home cache to acknowledge that it has processed
-	 * all the flush-and-invalidate requests.  This does not mean
-	 * that the flushed data has reached the memory controller yet,
-	 * but it does mean the home cache is processing the flushes.
-	 */
-	__insn_mf();
-
-	/*
-	 * Issue a load to the last cache line, which can't complete
-	 * until all the previously-issued flushes to the same memory
-	 * controller have also completed.  If we weren't striping
-	 * memory, that one load would be sufficient, but since we may
-	 * be, we also need to back up to the last load issued to
-	 * another memory controller, which would be the point where
-	 * we crossed a "striping" boundary (the granularity of striping
-	 * across memory controllers).  Keep backing up and doing this
-	 * until we are before the beginning of the buffer, or have
-	 * hit all the controllers.
-	 *
-	 * If we are flushing a hash-for-home buffer, it's even worse.
-	 * Each line may be homed on a different tile, and each tile
-	 * may have up to four lines that are on different
-	 * controllers.  So as we walk backwards, we have to touch
-	 * enough cache lines to satisfy these constraints.  In
-	 * practice this ends up being close enough to "load from
-	 * every cache line on a full memory stripe on each
-	 * controller" that we simply do that, to simplify the logic.
-	 *
-	 * On TILE-Gx the hash-for-home function is much more complex,
-	 * with the upshot being we can't readily guarantee we have
-	 * hit both entries in the 128-entry AMT that were hit by any
-	 * load in the entire range, so we just re-load them all.
-	 * With larger buffers, we may want to consider using a hypervisor
-	 * trap to issue loads directly to each hash-for-home tile for
-	 * each controller (doing it from Linux would trash the TLB).
-	 */
-	if (hfh) {
-		step_size = L2_CACHE_BYTES;
-#ifdef __tilegx__
-		load_count = (size + L2_CACHE_BYTES - 1) / L2_CACHE_BYTES;
-#else
-		load_count = (STRIPE_WIDTH / L2_CACHE_BYTES) *
-			      (1 << CHIP_LOG_NUM_MSHIMS());
-#endif
-	} else {
-		step_size = STRIPE_WIDTH;
-		load_count = (1 << CHIP_LOG_NUM_MSHIMS());
-	}
-
-	/* Load the last byte of the buffer. */
-	p = (char *)buffer + size - 1;
-	force_load(p);
-
-	/* Bump down to the end of the previous stripe or cache line. */
-	p -= step_size;
-	p = (char *)((unsigned long)p | (step_size - 1));
-
-	/* Figure out how far back we need to go. */
-	base = p - (step_size * (load_count - 2));
-	if ((unsigned long)base < (unsigned long)buffer)
-		base = buffer;
-
-	/* Fire all the loads we need. */
-	for (; p >= base; p -= step_size)
-		force_load(p);
-
-	/*
-	 * Repeat, but with finv's instead of loads, to get rid of the
-	 * data we just loaded into our own cache and the old home L3.
-	 * The finv's are guaranteed not to actually flush the data in
-	 * the buffer back to their home, since we just read it, so the
-	 * lines are clean in cache; we will only invalidate those lines.
-	 */
-	p = (char *)buffer + size - 1;
-	__insn_finv(p);
-	p -= step_size;
-	p = (char *)((unsigned long)p | (step_size - 1));
-	for (; p >= base; p -= step_size)
-		__insn_finv(p);
-
-	/* Wait for these finv's (and thus the first finvs) to be done. */
-	__insn_mf();
-
-#ifdef __tilegx__
-	/* Reenable the prefetcher. */
-	__insn_mtspr(SPR_DSTREAM_PF, old_dstream_pf);
-#endif
-}
-EXPORT_SYMBOL_GPL(finv_buffer_remote);
diff --git a/arch/tile/lib/checksum.c b/arch/tile/lib/checksum.c
deleted file mode 100644
index c3ca3e64d9d9..000000000000
--- a/arch/tile/lib/checksum.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- *   This program is free software; you can redistribute it and/or
- *   modify it under the terms of the GNU General Public License
- *   as published by the Free Software Foundation, version 2.
- *
- *   This program is distributed in the hope that it will be useful, but
- *   WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- *   NON INFRINGEMENT.  See the GNU General Public License for
- *   more details.
- * Support code for the main lib/checksum.c.
- */
-
-#include <net/checksum.h>
-#include <linux/module.h>
-
-__wsum do_csum(const unsigned char *buff, int len)
-{
-	int odd, count;
-	unsigned long result = 0;
-
-	if (len <= 0)
-		goto out;
-	odd = 1 & (unsigned long) buff;
-	if (odd) {
-		result = (*buff << 8);
-		len--;
-		buff++;
-	}
-	count = len >> 1;		/* nr of 16-bit words.. */
-	if (count) {
-		if (2 & (unsigned long) buff) {
-			result += *(const unsigned short *)buff;
-			count--;
-			len -= 2;
-			buff += 2;
-		}
-		count >>= 1;		/* nr of 32-bit words.. */
-		if (count) {
-#ifdef __tilegx__
-			if (4 & (unsigned long) buff) {
-				unsigned int w = *(const unsigned int *)buff;
-				result = __insn_v2sadau(result, w, 0);
-				count--;
-				len -= 4;
-				buff += 4;
-			}
-			count >>= 1;		/* nr of 64-bit words.. */
-#endif
-
-			/*
-			 * This algorithm could wrap around for very
-			 * large buffers, but those should be impossible.
-			 */
-			BUG_ON(count >= 65530);
-
-			while (count) {
-				unsigned long w = *(const unsigned long *)buff;
-				count--;
-				buff += sizeof(w);
-#ifdef __tilegx__
-				result = __insn_v2sadau(result, w, 0);
-#else
-				result = __insn_sadah_u(result, w, 0);
-#endif
-			}
-#ifdef __tilegx__
-			if (len & 4) {
-				unsigned int w = *(const unsigned int *)buff;
-				result = __insn_v2sadau(result, w, 0);
-				buff += 4;
-			}
-#endif
-		}
-		if (len & 2) {
-			result += *(const unsigned short *) buff;
-			buff += 2;
-		}
-	}
-	if (len & 1)
-		result += *buff;
-	result = csum_long(result);
-	if (odd)
-		result = swab16(result);
-out:
-	return result;
-}
diff --git a/arch/tile/lib/cpumask.c b/arch/tile/lib/cpumask.c
deleted file mode 100644
index 75947edccb26..000000000000
--- a/arch/tile/lib/cpumask.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- *   This program is free software; you can redistribute it and/or
- *   modify it under the terms of the GNU General Public License
- *   as published by the Free Software Foundation, version 2.
- *
- *   This program is distributed in the hope that it will be useful, but
- *   WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- *   NON INFRINGEMENT.  See the GNU General Public License for
- *   more details.
- */
-
-#include <linux/cpumask.h>
-#include <linux/ctype.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-#include <linux/export.h>
-
-/*
- * Allow cropping out bits beyond the end of the array.
- * Move to "lib" directory if more clients want to use this routine.
- */
-int bitmap_parselist_crop(const char *bp, unsigned long *maskp, int nmaskbits)
-{
-	unsigned a, b;
-
-	bitmap_zero(maskp, nmaskbits);
-	do {
-		if (!isdigit(*bp))
-			return -EINVAL;
-		a = simple_strtoul(bp, (char **)&bp, 10);
-		b = a;
-		if (*bp == '-') {
-			bp++;
-			if (!isdigit(*bp))
-				return -EINVAL;
-			b = simple_strtoul(bp, (char **)&bp, 10);
-		}
-		if (!(a <= b))
-			return -EINVAL;
-		if (b >= nmaskbits)
-			b = nmaskbits-1;
-		while (a <= b) {
-			set_bit(a, maskp);
-			a++;
-		}
-		if (*bp == ',')
-			bp++;
-	} while (*bp != '\0' && *bp != '\n');
-	return 0;
-}
-EXPORT_SYMBOL(bitmap_parselist_crop);
diff --git a/arch/tile/lib/delay.c b/arch/tile/lib/delay.c
deleted file mode 100644
index cdacdd11d360..000000000000
--- a/arch/tile/lib/delay.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- *   This program is free software; you can redistribute it and/or
- *   modify it under the terms of the GNU General Public License
- *   as published by the Free Software Foundation, version 2.
- *
- *   This program is distributed in the hope that it will be useful, but
- *   WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- *   NON INFRINGEMENT.  See the GNU General Public License for
- *   more details.
- */
-
-#include <linux/module.h>
-#include <linux/delay.h>
-#include <linux/thread_info.h>
-#include <asm/timex.h>
-
-void __udelay(unsigned long usecs)
-{
-	if (usecs > ULONG_MAX / 1000) {
-		WARN_ON_ONCE(usecs > ULONG_MAX / 1000);
-		usecs = ULONG_MAX / 1000;
-	}
-	__ndelay(usecs * 1000);
-}
-EXPORT_SYMBOL(__udelay);
-
-void __ndelay(unsigned long nsecs)
-{
-	cycles_t target = get_cycles();
-	target += ns2cycles(nsecs);
-	whil