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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2021-08-30 15:20:05 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2021-08-30 15:20:05 -0700 |
| commit | ccd8ec4a3f9a5d3d97766231b04e7321dcc2df1e (patch) | |
| tree | f18dba3d38dccff8a71257d9218d380cb7638add /arch/x86/kernel/apic/vector.c | |
| parent | 0a096f240aa1992ddac65f8e704f7b0c0795fe1c (diff) | |
| parent | 34739a2809e1e5d54d41d93cfc6b074e8d781ee2 (diff) | |
| download | linux-ccd8ec4a3f9a5d3d97766231b04e7321dcc2df1e.tar.gz linux-ccd8ec4a3f9a5d3d97766231b04e7321dcc2df1e.tar.bz2 linux-ccd8ec4a3f9a5d3d97766231b04e7321dcc2df1e.zip | |
Merge tag 'x86-irq-2021-08-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 PIRQ updates from Thomas Gleixner:
"A set of updates to support port 0x22/0x23 based PCI configuration
space which can be found on various ALi chipsets and is also available
on older Intel systems which expose a PIRQ router.
While the Intel support is more or less nostalgia, the ALi chips are
still in use on popular embedded boards used for routers"
* tag 'x86-irq-2021-08-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86: Fix typo s/ECLR/ELCR/ for the PIC register
x86: Avoid magic number with ELCR register accesses
x86/PCI: Add support for the Intel 82426EX PIRQ router
x86/PCI: Add support for the Intel 82374EB/82374SB (ESC) PIRQ router
x86/PCI: Add support for the ALi M1487 (IBC) PIRQ router
x86: Add support for 0x22/0x23 port I/O configuration space
Diffstat (limited to 'arch/x86/kernel/apic/vector.c')
| -rw-r--r-- | arch/x86/kernel/apic/vector.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c index fb67ed5e7e6a..c132daabe615 100644 --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -1299,7 +1299,7 @@ static void __init print_PIC(void) pr_debug("... PIC ISR: %04x\n", v); - v = inb(0x4d1) << 8 | inb(0x4d0); + v = inb(PIC_ELCR2) << 8 | inb(PIC_ELCR1); pr_debug("... PIC ELCR: %04x\n", v); } |