Merge branch 'pci/controller/kconfig'

- Use uniform language in Kconfig menu entries (Bjorn Helgaas)

- Sort controller Kconfig entries by vendor (Bjorn Helgaas)

* pci/controller/kconfig:
  PCI: xilinx: Drop obsolete dependency on COMPILE_TEST
  PCI: mobiveil: Sort Kconfig entries by vendor
  PCI: dwc: Sort Kconfig entries by vendor
  PCI: Sort controller Kconfig entries by vendor
  PCI: Use consistent controller Kconfig menu entry language
  PCI: xilinx-nwl: Add 'Xilinx' to Kconfig prompt
  PCI: hv: Add 'Microsoft' to Kconfig prompt
  PCI: meson: Add 'Amlogic' to Kconfig prompt
  PCI: Use of_property_present() for testing DT property presence
  PCI/PM: Extend D3hot delay for NVIDIA HDA controllers
  dt-bindings: PCI: qcom: Document msi-map and msi-map-mask properties
  PCI: qcom: Add SM8550 PCIe support
  dt-bindings: PCI: qcom: Add SM8550 compatible
  PCI: qcom: Add support for SDX55 SoC
  dt-bindings: PCI: qcom-ep: Fix the unit address used in example
  dt-bindings: PCI: qcom: Add SDX55 SoC
  dt-bindings: PCI: qcom: Update maintainers entry
  PCI: qcom: Enable async probe by default
  PCI: qcom: Add support for system suspend and resume
  PCI/PM: Drop pci_bridge_wait_for_secondary_bus() timeout parameter
  PCI/PM: Increase wait time after resume
  PCI: pciehp: Fix AB-BA deadlock between reset_lock and device_lock
  PCI: Fix up L1SS capability for Intel Apollo Lake Root Port
  PCI: qcom: Expose link transition counts via debugfs
  dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs
  PCI: qcom: Rename qcom_pcie_config_sid_sm8250() to reflect IP version
  PCI: qcom: Use macros for defining total no. of clocks & supplies
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.3.3
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0
  PCI: qcom: Use lower case for hex
  PCI: qcom: Add missing macros for register fields
  PCI: qcom: Use bitfield definitions for register fields
  PCI: qcom: Sort and group registers and bitfield definitions
  PCI: qcom: Remove PCIE20_ prefix from register definitions
  PCI: qcom: Fix the incorrect register usage in v2.7.0 config
  PCI/EDR: Add edr_handle_event() comments
  PCI/EDR: Clear Device Status after EDR error recovery
  efi/cper: Remove unnecessary aer.h include
  dt-bindings: imx6q-pcie: Restruct i.MX PCIe schema
  PCI/P2PDMA: Fix pci_p2pmem_find_many() kernel-doc
  EISA: Drop unused pci_bus_for_each_resource() index argument
  PCI: Make pci_bus_for_each_resource() index optional
  PCI: Document pci_bus_for_each_resource()
  PCI: Introduce pci_dev_for_each_resource()
  PCI: Introduce pci_resource_n()
  PCI: ixp4xx: Use PCI_CONF1_ADDRESS() macro
  PCI: mt7621: Use dev_info() to log PCIe card detection
  PCI: imx6: Install the fault handler only on compatible match
  PCI: layerscape: Add EP mode support for ls1028a
  PCI: rcar: Avoid defines prefixed with CONFIG
  dt-bindings: PCI: convert amlogic,meson-pcie.txt to dt-schema
  PCI: kirin: Select REGMAP_MMIO

1 files changed, 59 insertions, 0 deletions

diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index 615a76d70019..c6c46605812b 100644
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -824,3 +824,62 @@ static void rs690_fix_64bit_dma(struct pci_dev *pdev)
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7910, rs690_fix_64bit_dma);
 
 #endif
+
+/*
+ * When returning from D3cold to D0, firmware on some Google Coral and Reef
+ * family Chromebooks with Intel Apollo Lake SoC clobbers the headers of
+ * both the L1 PM Substates capability and the previous capability for the
+ * "Celeron N3350/Pentium N4200/Atom E3900 Series PCI Express Port B #1".
+ *
+ * Save those values at enumeration-time and restore them at resume.
+ */
+
+static u16 prev_cap, l1ss_cap;
+static u32 prev_header, l1ss_header;
+
+static void chromeos_save_apl_pci_l1ss_capability(struct pci_dev *dev)
+{
+	int pos = PCI_CFG_SPACE_SIZE, prev = 0;
+	u32 header, pheader = 0;
+
+	while (pos) {
+		pci_read_config_dword(dev, pos, &header);
+		if (PCI_EXT_CAP_ID(header) == PCI_EXT_CAP_ID_L1SS) {
+			prev_cap = prev;
+			prev_header = pheader;
+			l1ss_cap = pos;
+			l1ss_header = header;
+			return;
+		}
+
+		prev = pos;
+		pheader = header;
+		pos = PCI_EXT_CAP_NEXT(header);
+	}
+}
+
+static void chromeos_fixup_apl_pci_l1ss_capability(struct pci_dev *dev)
+{
+	u32 header;
+
+	if (!prev_cap || !prev_header || !l1ss_cap || !l1ss_header)
+		return;
+
+	/* Fixup the header of L1SS Capability if missing */
+	pci_read_config_dword(dev, l1ss_cap, &header);
+	if (header != l1ss_header) {
+		pci_write_config_dword(dev, l1ss_cap, l1ss_header);
+		pci_info(dev, "restore L1SS Capability header (was %#010x now %#010x)\n",
+			 header, l1ss_header);
+	}
+
+	/* Fixup the link to L1SS Capability if missing */
+	pci_read_config_dword(dev, prev_cap, &header);
+	if (header != prev_header) {
+		pci_write_config_dword(dev, prev_cap, prev_header);
+		pci_info(dev, "restore previous Capability header (was %#010x now %#010x)\n",
+			 header, prev_header);
+	}
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_save_apl_pci_l1ss_capability);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_fixup_apl_pci_l1ss_capability);