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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-14 13:49:00 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-08-03 08:49:00 +0200 |
| commit | 89089daa0a0dcdc22c33e3b9bd9077726ff7a32d (patch) | |
| tree | f81469a55e20c833c80af2d3c209dc900f7bb3e0 /arch | |
| parent | c33ceabc98f5232bdec5f7c8f6b939559c610fb6 (diff) | |
| download | linux-89089daa0a0dcdc22c33e3b9bd9077726ff7a32d.tar.gz linux-89089daa0a0dcdc22c33e3b9bd9077726ff7a32d.tar.bz2 linux-89089daa0a0dcdc22c33e3b9bd9077726ff7a32d.zip | |
arm64: dts: renesas: r8a779g0: Add L3 cache controller
[ Upstream commit f08407210db921a4c9eaeaa92d0c434858b9c6c4 ]
Describe the cache configuration for the first Cortex-A76 CPU core on
the Renesas R-Car V4H (R8A779G0) SoC.
Extracted from a larger patch in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/dfd743b32198295afb78bc0ac337ef283fa3879a.1668429870.git.geert+renesas@glider.be
Stable-dep-of: 6fca24a07e1d ("arm64: dts: renesas: r8a779a0: Add missing hypervisor virtual timer IRQ")
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 868d1a3cbdf6..9f6a30cf315f 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -23,6 +23,14 @@ reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779G0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA76_0>; + }; + + L3_CA76_0: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A779G0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; }; }; |