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| author | Marc Zyngier <maz@kernel.org> | 2024-05-24 15:19:56 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-06-16 13:41:37 +0200 |
| commit | e0032f5c086d3e28a7ed2e247fba6ab6517877c6 (patch) | |
| tree | d45d92605cf6b54a40aa320571c20be16f47656e /crypto | |
| parent | 5b12ce0b6fd9956c6825f04fb00544ff8d302bd4 (diff) | |
| download | linux-e0032f5c086d3e28a7ed2e247fba6ab6517877c6.tar.gz linux-e0032f5c086d3e28a7ed2e247fba6ab6517877c6.tar.bz2 linux-e0032f5c086d3e28a7ed2e247fba6ab6517877c6.zip | |
KVM: arm64: AArch32: Fix spurious trapping of conditional instructions
commit c92e8b9eacebb4060634ebd9395bba1b29aadc68 upstream.
We recently upgraded the view of ESR_EL2 to 64bit, in keeping with
the requirements of the architecture.
However, the AArch32 emulation code was left unaudited, and the
(already dodgy) code that triages whether a trap is spurious or not
(because the condition code failed) broke in a subtle way:
If ESR_EL2.ISS2 is ever non-zero (unlikely, but hey, this is the ARM
architecture we're talking about), the hack that tests the top bits
of ESR_EL2.EC will break in an interesting way.
Instead, use kvm_vcpu_trap_get_class() to obtain the EC, and list
all the possible ECs that can fail a condition code check.
While we're at it, add SMC32 to the list, as it is explicitly listed
as being allowed to trap despite failing a condition code check (as
described in the HCR_EL2.TSC documentation).
Fixes: 0b12620fddb8 ("KVM: arm64: Treat ESR_EL2 as a 64-bit register")
Cc: stable@vger.kernel.org
Acked-by: Oliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20240524141956.1450304-4-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'crypto')
0 files changed, 0 insertions, 0 deletions
