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| author | Cheng Ming Lin <chengminglin@mxic.com.tw> | 2024-11-12 15:52:42 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-12-14 19:54:02 +0100 |
| commit | 1050f5871588b469af8b1c8a4495ab867b1454e2 (patch) | |
| tree | 559f226a620bbca870c537700cc4c58fc1fd68ce /drivers/cpufreq/mediatek-cpufreq-hw.c | |
| parent | f69123bb5c79fd9c85f6be5fa4571e7561708330 (diff) | |
| download | linux-1050f5871588b469af8b1c8a4495ab867b1454e2.tar.gz linux-1050f5871588b469af8b1c8a4495ab867b1454e2.tar.bz2 linux-1050f5871588b469af8b1c8a4495ab867b1454e2.zip | |
mtd: spi-nor: core: replace dummy buswidth from addr to data
commit 98d1fb94ce75f39febd456d6d3cbbe58b6678795 upstream.
The default dummy cycle for Macronix SPI NOR flash in Octal Output
Read Mode(1-1-8) is 20.
Currently, the dummy buswidth is set according to the address bus width.
In the 1-1-8 mode, this means the dummy buswidth is 1. When converting
dummy cycles to bytes, this results in 20 x 1 / 8 = 2 bytes, causing the
host to read data 4 cycles too early.
Since the protocol data buswidth is always greater than or equal to the
address buswidth. Setting the dummy buswidth to match the data buswidth
increases the likelihood that the dummy cycle-to-byte conversion will be
divisible, preventing the host from reading data prematurely.
Fixes: 0e30f47232ab ("mtd: spi-nor: add support for DTR protocol")
Cc: stable@vger.kernel.org
Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
Signed-off-by: Cheng Ming Lin <chengminglin@mxic.com.tw>
Link: https://lore.kernel.org/r/20241112075242.174010-2-linchengming884@gmail.com
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/cpufreq/mediatek-cpufreq-hw.c')
0 files changed, 0 insertions, 0 deletions