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| author | Stanley Chang <stanley_chang@realtek.com> | 2023-09-12 12:19:02 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2023-10-02 14:05:53 +0200 |
| commit | e72fc8d6a12af7ae8dd1b52cf68ed68569d29f80 (patch) | |
| tree | bc5bf9aeb9d8c316af290d3aa045480d743bf7a7 /drivers/fpga/stratix10-soc.c | |
| parent | a3d19c289bedc99f01010020074f00b60640ade8 (diff) | |
| download | linux-e72fc8d6a12af7ae8dd1b52cf68ed68569d29f80.tar.gz linux-e72fc8d6a12af7ae8dd1b52cf68ed68569d29f80.tar.bz2 linux-e72fc8d6a12af7ae8dd1b52cf68ed68569d29f80.zip | |
usb: dwc3: core: configure TX/RX threshold for DWC3_IP
In Synopsys's dwc3 data book:
To avoid underrun and overrun during the burst, in a high-latency bus
system (like USB), threshold and burst size control is provided through
GTXTHRCFG and GRXTHRCFG registers.
In Realtek DHC SoC, DWC3 USB 3.0 uses AHB system bus. When dwc3 is
connected with USB 2.5G Ethernet, there will be overrun problem.
Therefore, setting TX/RX thresholds can avoid this issue.
Signed-off-by: Stanley Chang <stanley_chang@realtek.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/20230912041904.30721-1-stanley_chang@realtek.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/fpga/stratix10-soc.c')
0 files changed, 0 insertions, 0 deletions