Merge drm/drm-next into drm-intel-next

Sync to v6.10-rc3.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>

1 files changed, 37 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 3ecc7ef95172..cfec85563bc6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -718,6 +718,37 @@ extract_render_dcc_offset(struct amdgpu_device *adev,
 	return 0;
 }
 
+static int convert_tiling_flags_to_modifier_gfx12(struct amdgpu_framebuffer *afb)
+{
+	struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
+	const struct drm_format_info *format_info;
+	u64 modifier = 0;
+	int tile = 0;
+	int swizzle = 0;
+
+	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) {
+		tile = AMD_FMT_MOD_TILE_VER_GFX12;
+		swizzle =  AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE);
+	}
+
+	modifier =
+		AMD_FMT_MOD |
+		AMD_FMT_MOD_SET(TILE, swizzle) |
+		AMD_FMT_MOD_SET(TILE_VERSION,  tile) |
+		AMD_FMT_MOD_SET(DCC, 0) |
+		AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, 0);
+
+	format_info = amdgpu_lookup_format_info(afb->base.format->format,
+						modifier);
+	if (!format_info)
+		return -EINVAL;
+
+	afb->base.modifier = modifier;
+	afb->base.flags |= DRM_MODE_FB_MODIFIERS;
+
+	return 0;
+}
+
 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 {
 	struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
@@ -742,6 +773,12 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 		int pipes = ilog2(num_pipes);
 		uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
 
+
+		if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) {
+			convert_tiling_flags_to_modifier_gfx12(afb);
+			return 0;
+		}
+
 		switch (swizzle >> 2) {
 		case 0: /* 256B */
 			block_size_bits = 8;