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| author | Andrey Grodzovsky <andrey.grodzovsky@amd.com> | 2019-05-01 10:57:14 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-08-27 09:17:35 -0500 |
| commit | 691bac9d093b13abf39f95bd82db0430a152246c (patch) | |
| tree | cffdc737b07aefda49bf2432c055414df78bba8c /drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | |
| parent | 6acaa6af1501d17d40bb9aa5d76d5bb0b4936ed9 (diff) | |
| download | linux-691bac9d093b13abf39f95bd82db0430a152246c.tar.gz linux-691bac9d093b13abf39f95bd82db0430a152246c.tar.bz2 linux-691bac9d093b13abf39f95bd82db0430a152246c.zip | |
drm/amdgpu: Vega20 SMU I2C HW engine controller.
Implement HW I2C enigne controller to be used by the RAS EEPROM
table manager. This is based on code from ATITOOLs.
v2:
Rename the file and all function prefixes to smu_v11_0_i2c
By Luben's observation always fill the TX fifo to full so
we don't have garbadge interpreted by the slave as valid data.
v3:
Remove preemption disable as the HW I2C controller will not
stop the clock on empty TX fifo and so it's not critical to
keep not empty queue.
Switch to fast mode 400 khz SCL clock for faster read and write.
v5:
Restore clock gating before releasing I2C bus and fix some
style comments.
v6:
squash in warning fix, fix includes (Alex)
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Luben Tuikov <Luben.Tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index b544e0a05925..86110e6095cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -25,6 +25,7 @@ #include "amdgpu.h" #include "amdgpu_ras.h" #include <linux/bits.h> +#include "smu_v11_0_i2c.h" #define EEPROM_I2C_TARGET_ADDR 0xA0 @@ -118,7 +119,7 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) switch (adev->asic_type) { case CHIP_VEGA20: - /*TODO Add MI-60 */ + ret = smu_v11_0_i2c_eeprom_control_init(&control->eeprom_accessor); break; default: @@ -170,7 +171,7 @@ void amdgpu_ras_eeprom_fini(struct amdgpu_ras_eeprom_control *control) switch (adev->asic_type) { case CHIP_VEGA20: - /*TODO Add MI-60 */ + smu_v11_0_i2c_eeprom_control_fini(&control->eeprom_accessor); break; default: |