diff options
| author | Maxime Ripard <maxime.ripard@bootlin.com> | 2019-07-22 21:24:10 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2019-07-22 21:24:10 +0200 |
| commit | 03b0f2ce735e97e9f49790d4563c82515b8fa702 (patch) | |
| tree | da561805bffd06bfba81c867f83cacb28f3a64e5 /drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | |
| parent | e4f86e43716443e934d705952902d40de0fa9a05 (diff) | |
| parent | 5f9e832c137075045d15cd6899ab0505cfb2ca4b (diff) | |
| download | linux-03b0f2ce735e97e9f49790d4563c82515b8fa702.tar.gz linux-03b0f2ce735e97e9f49790d4563c82515b8fa702.tar.bz2 linux-03b0f2ce735e97e9f49790d4563c82515b8fa702.zip | |
Merge v5.3-rc1 into drm-misc-next
Noralf needs some SPI patches in 5.3 to merge some work on tinydrm.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index cdddce938bf5..4410c97ac9b7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -29,8 +29,8 @@ #include <drm/drm_print.h> /* max number of rings */ -#define AMDGPU_MAX_RINGS 23 -#define AMDGPU_MAX_GFX_RINGS 1 +#define AMDGPU_MAX_RINGS 24 +#define AMDGPU_MAX_GFX_RINGS 2 #define AMDGPU_MAX_COMPUTE_RINGS 8 #define AMDGPU_MAX_VCE_RINGS 3 #define AMDGPU_MAX_UVD_ENC_RINGS 2 @@ -172,6 +172,7 @@ struct amdgpu_ring_funcs { enum drm_sched_priority priority); /* Try to soft recover the ring to make the fence signal */ void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid); + int (*preempt_ib)(struct amdgpu_ring *ring); }; struct amdgpu_ring { @@ -206,6 +207,10 @@ struct amdgpu_ring { unsigned fence_offs; uint64_t current_ctx; char name[16]; + u32 trail_seq; + unsigned trail_fence_offs; + u64 trail_fence_gpu_addr; + volatile u32 *trail_fence_cpu_addr; unsigned cond_exe_offs; u64 cond_exe_gpu_addr; volatile u32 *cond_exe_cpu_addr; @@ -246,6 +251,7 @@ struct amdgpu_ring { #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) +#define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r) int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); @@ -266,6 +272,12 @@ void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, struct dma_fence *fence); +static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring, + bool cond_exec) +{ + *ring->cond_exe_cpu_addr = cond_exec; +} + static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) { int i = 0; |