Merge tag 'drm-fixes-2024-08-10' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
 "Weekly regular fixes, mostly amdgpu with i915/xe having a few each,
  and then some misc bits across the board, seems about right for rc3
  time.

  client:
   - fix null ptr deref

  bridge:
   - connector: fix double free

  atomic:
   - fix async flip update

  panel:
   - document panel

  omap:
   - add config dependency

  tests:
   - fix gem shmem test

  drm buddy:
   - Add start address to trim function

  amdgpu:
   - DMCUB fix
   - Fix DET programming on some DCNs
   - DCC fixes
   - DCN 4.0.1 fixes
   - SMU 14.0.x update
   - MMHUB fix
   - DCN 3.1.4 fix
   - GC 12.0 fixes
   - Fix soft recovery error propogation
   - SDMA 7.0 fixes
   - DSC fix

  xe:
   - Fix off-by-one when processing RTP rules
   - Use dma_fence_chain_free in chain fence unused as a sync
   - Fix PL1 disable flow in xe_hwmon_power_max_write
   - Take ref to VM in delayed dump snapshot

  i915:
   - correct dual pps handling for MTL_PCH+ [display]
   - Adjust vma offset for framebuffer mmap offset [gem]
   - Fix Virtual Memory mapping boundaries calculation [gem]
   - Allow evicting to use the requested placement
   - Attempt to get pages without eviction first"

* tag 'drm-fixes-2024-08-10' of https://gitlab.freedesktop.org/drm/kernel: (31 commits)
  drm/xe: Take ref to VM in delayed snapshot
  drm/xe/hwmon: Fix PL1 disable flow in xe_hwmon_power_max_write
  drm/xe: Use dma_fence_chain_free in chain fence unused as a sync
  drm/xe/rtp: Fix off-by-one when processing rules
  drm/amdgpu: Add DCC GFX12 flag to enable address alignment
  drm/amdgpu: correct sdma7 max dw
  drm/amdgpu: Add address alignment support to DCC buffers
  drm/amd/display: Skip Recompute DSC Params if no Stream on Link
  drm/amdgpu: change non-dcc buffer copy configuration
  drm/amdgpu: Forward soft recovery errors to userspace
  drm/amdgpu: add golden setting for gc v12
  drm/buddy: Add start address support to trim function
  drm/amd/display: Add missing program DET segment call to pipe init
  drm/amd/display: Add missing DCN314 to the DML Makefile
  drm/amdgpu: force to use legacy inv in mmhub
  drm/amd/pm: update powerplay structure on smu v14.0.2/3
  drm/amd/display: Add missing mcache registers
  drm/amd/display: Add dcc propagation value
  drm/amd/display: Add missing DET segments programming
  drm/amd/display: Replace dm_execute_dmub_cmd with dc_wake_and_execute_dmub_cmd
  ...

1 files changed, 18 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
index fd3ac483760e..26efce9aa410 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
@@ -542,6 +542,23 @@ static unsigned gmc_v12_0_get_vbios_fb_size(struct amdgpu_device *adev)
 	return 0;
 }
 
+static unsigned int gmc_v12_0_get_dcc_alignment(struct amdgpu_device *adev)
+{
+	unsigned int max_tex_channel_caches, alignment;
+
+	if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 0) &&
+	    amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 1))
+		return 0;
+
+	max_tex_channel_caches = adev->gfx.config.max_texture_channel_caches;
+	if (is_power_of_2(max_tex_channel_caches))
+		alignment = (unsigned int)(max_tex_channel_caches / SZ_4);
+	else
+		alignment = roundup_pow_of_two(max_tex_channel_caches);
+
+	return (unsigned int)(alignment * max_tex_channel_caches * SZ_1K);
+}
+
 static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = {
 	.flush_gpu_tlb = gmc_v12_0_flush_gpu_tlb,
 	.flush_gpu_tlb_pasid = gmc_v12_0_flush_gpu_tlb_pasid,
@@ -551,6 +568,7 @@ static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = {
 	.get_vm_pde = gmc_v12_0_get_vm_pde,
 	.get_vm_pte = gmc_v12_0_get_vm_pte,
 	.get_vbios_fb_size = gmc_v12_0_get_vbios_fb_size,
+	.get_dcc_alignment = gmc_v12_0_get_dcc_alignment,
 };
 
 static void gmc_v12_0_set_gmc_funcs(struct amdgpu_device *adev)