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| author | Jack Xiao <Jack.Xiao@amd.com> | 2024-04-10 14:00:41 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-05-02 16:18:14 -0400 |
| commit | ad5c0a79dfca06ee7f1d5a9cf4f6b4a2113f5d04 (patch) | |
| tree | 65e3750d6afa0e5fa308d79274f93a0cff0733d7 /drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | |
| parent | fcc5df722dbc47c3a84386a1c70647cfe153e65d (diff) | |
| download | linux-ad5c0a79dfca06ee7f1d5a9cf4f6b4a2113f5d04.tar.gz linux-ad5c0a79dfca06ee7f1d5a9cf4f6b4a2113f5d04.tar.bz2 linux-ad5c0a79dfca06ee7f1d5a9cf4f6b4a2113f5d04.zip | |
drm/amdgpu/mes12: add legacy setting hw resource interface
For unified mes fw, add the legacy interface to set hardware
resources.
v2: remove warning (Alex)
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/mes_v12_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index cf6dea13cc95..0b67ff9c0492 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -376,6 +376,22 @@ static int mes_v12_0_misc_op(struct amdgpu_mes *mes, offsetof(union MESAPI__MISC, api_status)); } +static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes) +{ + union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; + + memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); + + mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; + mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100; + + return mes_v12_0_submit_pkt_and_poll_completion(mes, + &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), + offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); +} + static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes) { int i; @@ -424,7 +440,6 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes) mes_set_hw_res_pkt.enable_reg_active_poll = 1; mes_set_hw_res_pkt.oversubscription_timer = 50; - mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr; @@ -1043,7 +1058,7 @@ static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev) ring = &adev->gfx.kiq[0].ring; ring->me = 3; - ring->pipe = 1; + ring->pipe = adev->enable_uni_mes ? 0 : 1; ring->queue = 0; ring->adev = NULL; @@ -1309,6 +1324,9 @@ static int mes_v12_0_hw_init(void *handle) if (r) goto failure; + if (adev->enable_uni_mes) + mes_v12_0_set_hw_resources_1(&adev->mes); + mes_v12_0_init_aggregated_doorbell(&adev->mes); /* Enable the MES to handle doorbell ring on unmapped queue */ |