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| author | Qingqing Zhuo <Qingqing.Zhuo@amd.com> | 2023-08-03 00:49:48 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-08-30 15:51:13 -0400 |
| commit | 9d1870a7a4c73c781af03937a1bfa72aa7a4c7ea (patch) | |
| tree | 02a82ae2271b86e9301a3f680cbd2e68f6052b05 /drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | |
| parent | ccecb0796797671bb845c82b70cc43a2d89033a7 (diff) | |
| download | linux-9d1870a7a4c73c781af03937a1bfa72aa7a4c7ea.tar.gz linux-9d1870a7a4c73c781af03937a1bfa72aa7a4c7ea.tar.bz2 linux-9d1870a7a4c73c781af03937a1bfa72aa7a4c7ea.zip | |
drm/amd/display: Update DCE for DCN35 support
[Why & How]
Update DCE files for DCN35 usage.
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index 86233f94db4a..2fefdf40612d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -681,6 +681,8 @@ struct dce_hwseq_registers { uint32_t DMU_MEM_PWR_CNTL; uint32_t DCHUBBUB_ARB_HOSTVM_CNTL; uint32_t HPO_TOP_HW_CONTROL; + uint32_t DMU_CLK_CNTL; + uint32_t DCCG_GATE_DISABLE_CNTL5; }; /* set field name */ #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ @@ -1167,12 +1169,29 @@ struct dce_hwseq_registers { type I2C_LIGHT_SLEEP_FORCE;\ type HPO_IO_EN; +#define HWSEQ_DCN35_REG_FIELD_LIST(type) \ + type DISPCLK_R_DMU_GATE_DIS;\ + type DISPCLK_G_RBBMIF_GATE_DIS;\ + type RBBMIF_FGCG_REP_DIS;\ + type IHC_FGCG_REP_DIS;\ + type DPREFCLK_ALLOW_DS_CLKSTOP;\ + type DISPCLK_ALLOW_DS_CLKSTOP;\ + type DPPCLK_ALLOW_DS_CLKSTOP;\ + type DTBCLK_ALLOW_DS_CLKSTOP;\ + type DCFCLK_ALLOW_DS_CLKSTOP;\ + type DPIACLK_ALLOW_DS_CLKSTOP;\ + type LONO_FGCG_REP_DIS;\ + type LONO_DISPCLK_GATE_DISABLE;\ + type LONO_SOCCLK_GATE_DISABLE;\ + type LONO_DMCUBCLK_GATE_DISABLE; + struct dce_hwseq_shift { HWSEQ_REG_FIELD_LIST(uint8_t) HWSEQ_DCN_REG_FIELD_LIST(uint8_t) HWSEQ_DCN3_REG_FIELD_LIST(uint8_t) HWSEQ_DCN301_REG_FIELD_LIST(uint8_t) HWSEQ_DCN31_REG_FIELD_LIST(uint8_t) + HWSEQ_DCN35_REG_FIELD_LIST(uint8_t) }; struct dce_hwseq_mask { @@ -1181,6 +1200,7 @@ struct dce_hwseq_mask { HWSEQ_DCN3_REG_FIELD_LIST(uint32_t) HWSEQ_DCN301_REG_FIELD_LIST(uint32_t) HWSEQ_DCN31_REG_FIELD_LIST(uint32_t) + HWSEQ_DCN35_REG_FIELD_LIST(uint32_t) }; |