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| author | Jacky Liao <ziyu.liao@amd.com> | 2020-10-15 17:42:16 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-11-02 15:31:04 -0500 |
| commit | cae78e0331459643e21b982e4833a6525a43e498 (patch) | |
| tree | 9d7528c1c6260813f20e1d08729f61d9b969f753 /drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | |
| parent | 91bda9e9d248c749f99cc85538d16444507466f7 (diff) | |
| download | linux-cae78e0331459643e21b982e4833a6525a43e498.tar.gz linux-cae78e0331459643e21b982e4833a6525a43e498.tar.bz2 linux-cae78e0331459643e21b982e4833a6525a43e498.zip | |
drm/amd/display: Add OPTC memory low power support
[Why]
The OPTC memory blocks should be powered down when they are not in use.
This will reduce power consumption.
[How]
1. Set ODM_MEM_UNASSIGNED_PWR_MODE to shutdown memory when unassigned
2. Set ODM_MEM_VBLANK_PWR_MODE to light sleep mode when in vblank
3. Added a debug option to allow this behaviour to be turned off
4. Restructured debug options to use a bitfield in a way that's more clear
Signed-off-by: Jacky Liao <ziyu.liao@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index b77e22bf6aec..a8103c762c08 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -607,6 +607,10 @@ struct dce_hwseq_registers { uint32_t MC_VM_XGMI_LFB_CNTL; uint32_t AZALIA_AUDIO_DTO; uint32_t AZALIA_CONTROLLER_CLOCK_GATING; + #if defined(CONFIG_DRM_AMD_DC_DCN3_0) + uint32_t HPO_TOP_CLOCK_CONTROL; + uint32_t ODM_MEM_PWR_CTRL3; + #endif }; /* set field name */ #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ @@ -845,7 +849,9 @@ struct dce_hwseq_registers { #if defined(CONFIG_DRM_AMD_DC_DCN3_0) #define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\ HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \ - HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh) + HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ + HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ + HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh) #endif #if defined(CONFIG_DRM_AMD_DC_DCN3_01) @@ -1059,7 +1065,9 @@ struct dce_hwseq_registers { type D2VGA_MODE_ENABLE; \ type D3VGA_MODE_ENABLE; \ type D4VGA_MODE_ENABLE; \ - type AZALIA_AUDIO_DTO_MODULE; + type AZALIA_AUDIO_DTO_MODULE; \ + type ODM_MEM_UNASSIGNED_PWR_MODE; \ + type ODM_MEM_VBLANK_PWR_MODE; #if defined(CONFIG_DRM_AMD_DC_DCN3_0) #define HWSEQ_DCN3_REG_FIELD_LIST(type) \ |