diff options
| author | Webb Chen <yi-lchen@amd.com> | 2024-02-27 10:01:25 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-04-30 09:49:45 -0400 |
| commit | 4d4d3ff16db2642ade8b2fd64cb1abd65bddcf49 (patch) | |
| tree | a5bb0b06c29b553ddf26dd8e4f6687029fb03107 /drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c | |
| parent | a8ac994cf0693a1ce59410995594e56124a1c79f (diff) | |
| download | linux-4d4d3ff16db2642ade8b2fd64cb1abd65bddcf49.tar.gz linux-4d4d3ff16db2642ade8b2fd64cb1abd65bddcf49.tar.bz2 linux-4d4d3ff16db2642ade8b2fd64cb1abd65bddcf49.zip | |
drm/amd/display: Keep VBios pixel rate div setting util next mode set
[why]
VBios & Driver may have differnet pixel rate div policy.
If the policy is not same and fast boot is enabled,
it would cause the pixel rate is too high
after driver only performs stream blank & unblank.
[how]
We would keep pixel rate div setting by VBios until next mode set.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Webb Chen <yi-lchen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c index 542ce3b7f9e4..934203ef52bb 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c @@ -151,6 +151,7 @@ static const struct hwseq_private_funcs dcn314_private_funcs = { .set_shaper_3dlut = dcn20_set_shaper_3dlut, .setup_hpo_hw_control = dcn31_setup_hpo_hw_control, .calculate_dccg_k1_k2_values = dcn314_calculate_dccg_k1_k2_values, + .calculate_pix_rate_divider = dcn314_calculate_pix_rate_divider, .set_pixels_per_cycle = dcn314_set_pixels_per_cycle, .resync_fifo_dccg_dio = dcn314_resync_fifo_dccg_dio, }; |