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| author | Daniel Miess <daniel.miess@amd.com> | 2024-04-23 15:45:59 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-05-13 15:47:08 -0400 |
| commit | c49e44ede5cdfe650c2f769d8bd58cbe289e87cd (patch) | |
| tree | c9f981f3bbfcab36ef1f33f6ff5ef0a4cf96b2d9 /drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c | |
| parent | 4655b4d953067c176ecdbee4167cc85fc0058be1 (diff) | |
| download | linux-c49e44ede5cdfe650c2f769d8bd58cbe289e87cd.tar.gz linux-c49e44ede5cdfe650c2f769d8bd58cbe289e87cd.tar.bz2 linux-c49e44ede5cdfe650c2f769d8bd58cbe289e87cd.zip | |
drm/amd/display: Enable SYMCLK gating in DCCG
[WHY & HOW]
Enable root clock optimization for SYMCLK and only
disable it when it's actively used.
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c index 663bacd1fafd..0b6d7d76c85b 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c @@ -150,6 +150,7 @@ static const struct hwseq_private_funcs dcn35_private_funcs = { .dpp_root_clock_control = dcn35_dpp_root_clock_control, .dpstream_root_clock_control = dcn35_dpstream_root_clock_control, .physymclk_root_clock_control = dcn35_physymclk_root_clock_control, + .symclk_root_clock_control = dcn35_symclk_root_clock_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn35_update_odm, .set_hdr_multiplier = dcn10_set_hdr_multiplier, |