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| author | Martin Tsai <martin.tsai@amd.com> | 2023-12-18 16:36:44 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-01-09 15:43:53 -0500 |
| commit | 17e74e11ac2b46e7514705ae7abfb93ac0e20bd6 (patch) | |
| tree | 6c81731cfea6c3a5c4706bdb5143c6dc79b9eed0 /drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | |
| parent | 47bf0f83fc86df1bf42b385a91aadb910137c5c9 (diff) | |
| download | linux-17e74e11ac2b46e7514705ae7abfb93ac0e20bd6.tar.gz linux-17e74e11ac2b46e7514705ae7abfb93ac0e20bd6.tar.bz2 linux-17e74e11ac2b46e7514705ae7abfb93ac0e20bd6.zip | |
drm/amd/display: To adjust dprefclk by down spread percentage
[Why]
Panels show corruption with high refresh rate timings when ssc is
enabled.
[How]
Read down-spread percentage from lut to adjust dprefclk. Issues come
from S0i3 with this commit has been fixed by SMU.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Martin Tsai <martin.tsai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index cbba39d251e5..17e014d3bdc8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -333,6 +333,7 @@ struct clk_mgr { bool force_smu_not_present; bool dc_mode_softmax_enabled; int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes + int dp_dto_source_clock_in_khz; // Used to program DP DTO with ss adjustment on DCN314 int dentist_vco_freq_khz; struct clk_state_registers_and_bypass boot_snapshot; struct clk_bw_params *bw_params; |