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| author | Duncan Ma <duncan.ma@amd.com> | 2022-08-24 14:35:03 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-09-13 14:33:00 -0400 |
| commit | 247a94a627dbd9fed370b575288b874ef4a01991 (patch) | |
| tree | fce974ed325ffbeba4c201acb2f85e5b6469f979 /drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | |
| parent | e7dbdfa226ce621931a84f60e885d42c232fb990 (diff) | |
| download | linux-247a94a627dbd9fed370b575288b874ef4a01991.tar.gz linux-247a94a627dbd9fed370b575288b874ef4a01991.tar.bz2 linux-247a94a627dbd9fed370b575288b874ef4a01991.zip | |
drm/amd/display: Correct dram channel width for dcn314
[Why]
The interpretation of the number of memory channels
differ by memory type, and this affects channel width
for the DML input.
[How]
Set dram channel width according to memory type for
dcn314.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index 5d2b028e5dad..d9f1b0a4fbd4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -214,6 +214,7 @@ struct dummy_pstate_entry { struct clk_bw_params { unsigned int vram_type; unsigned int num_channels; + unsigned int dram_channel_width_bytes; unsigned int dispclk_vco_khz; unsigned int dc_mode_softmax_memclk; struct clk_limit_table clk_table; |