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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2023-04-03 10:25:44 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2023-04-03 10:25:45 +0200 |
| commit | 1138398d71e8e583669fcec96784471332e488d4 (patch) | |
| tree | cc832e08796450735ef16b8b75298cd9bb011a88 /drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | |
| parent | 63758fec651f2fe7eab0c5a833f84795911c36e9 (diff) | |
| parent | feae1bd80ec69a3a0011ba1fb88994785f705e3e (diff) | |
| download | linux-1138398d71e8e583669fcec96784471332e488d4.tar.gz linux-1138398d71e8e583669fcec96784471332e488d4.tar.bz2 linux-1138398d71e8e583669fcec96784471332e488d4.zip | |
Merge tag 'amd-drm-next-6.4-2023-03-31' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-6.4-2023-03-31:
amdgpu:
- Misc code cleanups
- S4 fixes
- MES fixes
- SR-IOV fixes
- Link DC backlight to connector device rather than PCI device
- W=1 fixes
- ASPM quirk
- RAS fixes
- DC dynamic split fixes and enablement for remaining chips
- Navi1x SMU fix
- Initial NBIO 7.9 support
- Initial GC 9.4.3 support
- Initial GFXHUB 1.2 support
- Initial MMHUB 1.8 support
- DCN 3.1.5 fixes
- Initial DC FAMs infrastructure
- Add support for 6.75Gbps link rates
- Add sysfs nodes for secondary VCN clocks
amdkfd:
- Initial support for GC 9.4.3
radeon:
- Convert to client-based fbdev emulation
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230331221955.7896-1-alexander.deucher@amd.com
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index ce006762f257..ad6acd1b34e1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -148,18 +148,21 @@ struct dccg_funcs { struct dccg *dccg, int inst); -void (*set_pixel_rate_div)( - struct dccg *dccg, - uint32_t otg_inst, - enum pixel_rate_div k1, - enum pixel_rate_div k2); - -void (*set_valid_pixel_rate)( - struct dccg *dccg, - int ref_dtbclk_khz, - int otg_inst, - int pixclk_khz); + void (*set_pixel_rate_div)(struct dccg *dccg, + uint32_t otg_inst, + enum pixel_rate_div k1, + enum pixel_rate_div k2); + void (*set_valid_pixel_rate)( + struct dccg *dccg, + int ref_dtbclk_khz, + int otg_inst, + int pixclk_khz); + + void (*dpp_root_clock_control)( + struct dccg *dccg, + unsigned int dpp_inst, + bool clock_on); }; #endif //__DAL_DCCG_H__ |