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| author | Alex Deucher <alexander.deucher@amd.com> | 2020-11-02 15:37:34 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-11-04 17:11:37 -0500 |
| commit | 20f2ffe504728612d7b0c34e4f8280e34251e704 (patch) | |
| tree | ab97de569be30e009ba6e5087f3f6c775167e46c /drivers/gpu/drm/amd/display/include | |
| parent | aeee2a48ec9239790b7c9a5c14dfb2a12554322f (diff) | |
| download | linux-20f2ffe504728612d7b0c34e4f8280e34251e704.tar.gz linux-20f2ffe504728612d7b0c34e4f8280e34251e704.tar.bz2 linux-20f2ffe504728612d7b0c34e4f8280e34251e704.zip | |
drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)
Avoids confusion in configurations.
v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled
v3: rebase on latest code
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> (v1)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/include')
| -rw-r--r-- | drivers/gpu/drm/amd/display/include/dal_asic_id.h | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/include/dal_types.h | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h | 4 |
3 files changed, 0 insertions, 16 deletions
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index 2bf60ac2974f..33128ebbeb9f 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -203,17 +203,12 @@ enum { #define ASICREV_IS_NAVI12_P(eChipRev) ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0)) #define ASICREV_IS_NAVI14_M(eChipRev) ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN)) #define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < RAVEN1_F0)) -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) #define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) ((eChipRev >= NV_SIENNA_CICHLID_P_A0) && (eChipRev < NV_DIMGREY_CAVEFISH_P_A0)) -#endif -#if defined(CONFIG_DRM_AMD_DC_DCN3_02) #define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev) ((eChipRev >= NV_DIMGREY_CAVEFISH_P_A0) && (eChipRev < NV_UNKNOWN)) -#endif #define GREEN_SARDINE_A0 0xA1 #ifndef ASICREV_IS_GREEN_SARDINE #define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF)) #endif -#if defined(CONFIG_DRM_AMD_DC_DCN3_01) #define FAMILY_VGH 144 #define DEVICE_ID_VGH_163F 0x163F #define VANGOGH_A0 0x01 @@ -222,7 +217,6 @@ enum { #ifndef ASICREV_IS_VANGOGH #define ASICREV_IS_VANGOGH(eChipRev) ((eChipRev >= VANGOGH_A0) && (eChipRev < VANGOGH_UNKNOWN)) #endif -#endif /* * ASIC chip ID diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h index 3ed7b066a925..0d485802a2d0 100644 --- a/drivers/gpu/drm/amd/display/include/dal_types.h +++ b/drivers/gpu/drm/amd/display/include/dal_types.h @@ -51,15 +51,9 @@ enum dce_version { DCN_VERSION_1_01, DCN_VERSION_2_0, DCN_VERSION_2_1, -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) DCN_VERSION_3_0, -#endif -#if defined(CONFIG_DRM_AMD_DC_DCN3_01) DCN_VERSION_3_01, -#endif -#if defined(CONFIG_DRM_AMD_DC_DCN3_02) DCN_VERSION_3_02, -#endif DCN_VERSION_MAX }; diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h index 04dd546a143c..792652236c61 100644 --- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h +++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h @@ -284,7 +284,6 @@ struct ext_hdmi_settings { struct i2c_reg_info reg_settings_6g[3]; }; -#if defined(CONFIG_DRM_AMD_DC_DCN3_01) struct edp_info { uint16_t edp_backlight_pwm_hz; uint16_t edp_ss_percentage; @@ -295,7 +294,6 @@ struct edp_info { uint8_t edp_panel_bpc; uint8_t edp_bootup_bl_level; }; -#endif /* V6 */ struct integrated_info { @@ -415,11 +413,9 @@ struct integrated_info { struct i2c_reg_info dp3_ext_hdmi_6g_reg_settings[3]; /* V11 */ uint32_t dp_ss_control; -#if defined(CONFIG_DRM_AMD_DC_DCN3_01) /* V2.1 */ struct edp_info edp1_info; struct edp_info edp2_info; -#endif }; /** |