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| author | Boyuan Zhang <boyuan.zhang@amd.com> | 2018-07-18 16:13:29 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-08-27 11:10:09 -0500 |
| commit | 8709890892d839ba7169924a301c9cb0bd54ce6b (patch) | |
| tree | e3019d5662e13614b812b4e226b84f62d6da5d4a /drivers/gpu/drm/amd/include | |
| parent | eb4f6999203710f82861fd03c1bc696dae4182b5 (diff) | |
| download | linux-8709890892d839ba7169924a301c9cb0bd54ce6b.tar.gz linux-8709890892d839ba7169924a301c9cb0bd54ce6b.tar.bz2 linux-8709890892d839ba7169924a301c9cb0bd54ce6b.zip | |
drm/amdgpu: add system interrupt register offset header
Add new register offset for enabling system interrupt.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h index fe0cbaade3c3..216a401028de 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h @@ -307,6 +307,8 @@ #define mmUVD_LMI_CTRL2_BASE_IDX 1 #define mmUVD_MASTINT_EN 0x0540 #define mmUVD_MASTINT_EN_BASE_IDX 1 +#define mmUVD_SYS_INT_EN 0x0541 +#define mmUVD_SYS_INT_EN_BASE_IDX 1 #define mmJPEG_CGC_CTRL 0x0565 #define mmJPEG_CGC_CTRL_BASE_IDX 1 #define mmUVD_LMI_CTRL 0x0566 |