diff options
| author | Dave Airlie <airlied@redhat.com> | 2023-06-15 14:11:22 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2023-06-15 14:11:22 +1000 |
| commit | 901bdf5ea1a836400ee69aa32b04e9c209271ec7 (patch) | |
| tree | ccb1851c8a71e776dbccf1ccae132dc9b5f093c6 /drivers/gpu/drm/amd/include | |
| parent | ba57b9b11f78530146f02b776854b2b6b6d344a4 (diff) | |
| parent | 3b718dcaf163d17fe907ea098c8449e0cd6bc271 (diff) | |
| download | linux-901bdf5ea1a836400ee69aa32b04e9c209271ec7.tar.gz linux-901bdf5ea1a836400ee69aa32b04e9c209271ec7.tar.bz2 linux-901bdf5ea1a836400ee69aa32b04e9c209271ec7.zip | |
Merge tag 'amd-drm-next-6.5-2023-06-09' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-6.5-2023-06-02:
amdgpu:
- SR-IOV fixes
- Warning fixes
- Misc code cleanups and spelling fixes
- DCN 3.2 updates
- Improved DC FAMS support for better power management
- Improved DC SubVP support for better power management
- DCN 3.1.x fixes
- Max IB size query
- DC GPU reset fixes
- RAS updates
- DCN 3.0.x fixes
- S/G display fixes
- CP shadow buffer support
- Implement connector force callback
- Z8 power improvements
- PSP 13.0.10 vbflash support
- Mode2 reset fixes
- Store MQDs in VRAM to improve queue switch latency
- VCN 3.x fixes
- JPEG 3.x fixes
- Enable DC_FP on LoongArch
- GFXOFF fixes
- GC 9.4.3 partition support
- SDMA 4.4.2 partition support
- VCN/JPEG 4.0.3 partition support
- VCN 4.0.3 updates
- NBIO 7.9 updates
- GC 9.4.3 updates
- Take NUMA into account when allocating memory
- Handle NUMA for partitions
- SMU 13.0.6 updates
- GC 9.4.3 RAS updates
- Stop including unused swiotlb.h
- SMU 13.0.7 fixes
- Fix clock output ordering on some APUs
- Clean up DC FPGA code
- GFX9 preemption fixes
- Misc irq fixes
- S0ix fixes
- Add new DRM_AMDGPU_WERROR config parameter to help with CI
- PCIe fix for RDNA2
- kdoc fixes
- Documentation updates
amdkfd:
- Query TTM mem limit rather than hardcoding it
- GC 9.4.3 partition support
- Handle NUMA for partitions
radeon:
- Fix possible double free
- Stop including unused swiotlb.h
- Fix possible division by zero
ttm:
- Add query for TTM mem limit
- Add NUMA awareness to pools
- Export ttm_pool_fini()
UAPI:
- Add new ctx query flag to better handle GPU resets
Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290
- Add new interface to query and set shadow buffer for RDNA3
Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21986
- Add new INFO query for max IB size
Proposed userspace: https://gitlab.freedesktop.org/bnieuwenhuizen/mesa/-/commits/ib-rejection-v3
amd-drm-next-6.5-2023-06-09:
amdgpu:
- S0ix fixes
- Initial SMU13 Overdrive support
- kdoc fixes
- Misc clode cleanups
- Flexible array fixes
- Display OTG fixes
- SMU 13.0.6 updates
- Revert some broken clock counter updates
- Misc display fixes
- GFX9 preemption fixes
- Add support for newer EEPROM bad page table format
- Add missing radeon secondary id
- Add support for new colorspace KMS API
- CSA fix
- Stable pstate fixes for APUs
- make vbl interface admin only
- Handle PCI accelerator class
amdkfd:
- Add debugger support for gdb
radeon:
- Fix possible UAF
drm:
- Add Colorspace functionality
UAPI:
- Add debugger interface for enabling gdb
Proposed userspace: https://github.com/ROCm-Developer-Tools/ROCdbgapi/tree/wip-dbgapi
- Add KMS colorspace API
Discussion: https://lists.freedesktop.org/archives/dri-devel/2023-June/408128.html
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230609174817.7764-1-alexander.deucher@amd.com
Diffstat (limited to 'drivers/gpu/drm/amd/include')
22 files changed, 15788 insertions, 29 deletions
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index e4a22c68517d..f175e65b853a 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -240,7 +240,6 @@ enum DC_FEATURE_MASK { DC_DISABLE_LTTPR_DP2_0 = (1 << 6), //0x40, disabled by default DC_PSR_ALLOW_SMU_OPT = (1 << 7), //0x80, disabled by default DC_PSR_ALLOW_MULTI_DISP_OPT = (1 << 8), //0x100, disabled by default - DC_ENABLE_SUBVP_DRR = (1 << 9), // 0x200, disabled by default }; enum DC_DEBUG_MASK { diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h index 79c41004c0b6..4908044f7409 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h @@ -5194,6 +5194,20 @@ #define mmSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0 #define mmSPI_WCL_PIPE_PERCENT_CS7 0x1f70 #define mmSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0 +#define mmSPI_GDBG_WAVE_CNTL 0x1f71 +#define mmSPI_GDBG_WAVE_CNTL_BASE_IDX 0 +#define mmSPI_GDBG_TRAP_CONFIG 0x1f72 +#define mmSPI_GDBG_TRAP_CONFIG_BASE_IDX 0 +#define mmSPI_GDBG_TRAP_MASK 0x1f73 +#define mmSPI_GDBG_TRAP_MASK_BASE_IDX 0 +#define mmSPI_GDBG_WAVE_CNTL2 0x1f74 +#define mmSPI_GDBG_WAVE_CNTL2_BASE_IDX 0 +#define mmSPI_GDBG_WAVE_CNTL3 0x1f75 +#define mmSPI_GDBG_WAVE_CNTL3_BASE_IDX 0 +#define mmSPI_GDBG_TRAP_DATA0 0x1f78 +#define mmSPI_GDBG_TRAP_DATA0_BASE_IDX 0 +#define mmSPI_GDBG_TRAP_DATA1 0x1f79 +#define mmSPI_GDBG_TRAP_DATA1_BASE_IDX 0 #define mmSPI_COMPUTE_QUEUE_RESET 0x1f7b #define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 #define mmSPI_RESOURCE_RESERVE_CU_0 0x1f7c diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h index 52043e143067..9b7d219e7954 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h @@ -19700,6 +19700,75 @@ //SPI_WCL_PIPE_PERCENT_CS7 #define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 #define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL +//SPI_GDBG_WAVE_CNTL +#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1 +#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x00000001L +#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x0001FFFEL +//SPI_GDBG_TRAP_CONFIG +#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0 +#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4 +#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7 +#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9 +#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf +#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10 +#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x00000003L +#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0x0000000CL +#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x00000070L +#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x00000080L +#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x00000100L +#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x00000200L +#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x00008000L +#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xFFFF0000L +//SPI_GDBG_TRAP_MASK +#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0 +#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9 +#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x01FFL +#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x0200L +//SPI_GDBG_WAVE_CNTL2 +#define SPI_GDBG_WAVE_CNTL2__VMID_MASK__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL2__MODE__SHIFT 0x10 +#define SPI_GDBG_WAVE_CNTL2__VMID_MASK_MASK 0x0000FFFFL +#define SPI_GDBG_WAVE_CNTL2__MODE_MASK 0x00030000L +//SPI_GDBG_WAVE_CNTL3 +#define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT 0x1 +#define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT 0x2 +#define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT 0x3 +#define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT 0x4 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT 0x5 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT 0x6 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT 0x7 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT 0x8 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT 0x9 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa +#define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT 0xb +#define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT 0xc +#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT 0xd +#define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT 0x1c +#define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK 0x00000001L +#define SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK 0x00000002L +#define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK 0x00000004L +#define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK 0x00000008L +#define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK 0x00000010L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK 0x00000020L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK 0x00000040L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK 0x00000080L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK 0x00000100L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK 0x00000200L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK 0x00000400L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK 0x00000800L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK 0x00001000L +#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK 0x0FFFE000L +#define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK 0x10000000L +//SPI_GDBG_TRAP_DATA0 +#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0 +#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xFFFFFFFFL +//SPI_GDBG_TRAP_DATA1 +#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0 +#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xFFFFFFFFL //SPI_COMPUTE_QUEUE_RESET #define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h index a734abaa91a5..5e15ac14b63c 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h @@ -26,6 +26,8 @@ #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0 #define mmSQ_DEBUG_STS_GLOBAL2 0x10B0 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0 +#define mmSQ_DEBUG 0x10B1 +#define mmSQ_DEBUG_BASE_IDX 0 // addressBlock: gc_sdma0_sdma0dec // base address: 0x4980 @@ -4853,10 +4855,18 @@ #define mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 #define mmSPI_GDBG_WAVE_CNTL 0x1f71 #define mmSPI_GDBG_WAVE_CNTL_BASE_IDX 0 +#define mmSPI_GDBG_TRAP_CONFIG 0x1f72 +#define mmSPI_GDBG_TRAP_CONFIG_BASE_IDX 0 #define mmSPI_GDBG_TRAP_MASK 0x1f73 #define mmSPI_GDBG_TRAP_MASK_BASE_IDX 0 #define mmSPI_GDBG_WAVE_CNTL2 0x1f74 #define mmSPI_GDBG_WAVE_CNTL2_BASE_IDX 0 +#define mmSPI_GDBG_WAVE_CNTL3 0x1f75 +#define mmSPI_GDBG_WAVE_CNTL3_BASE_IDX 0 +#define mmSPI_GDBG_TRAP_DATA0 0x1f78 +#define mmSPI_GDBG_TRAP_DATA0_BASE_IDX 0 +#define mmSPI_GDBG_TRAP_DATA1 0x1f79 +#define mmSPI_GDBG_TRAP_DATA1_BASE_IDX 0 #define mmSPI_COMPUTE_QUEUE_RESET 0x1f7b #define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 #define mmSPI_RESOURCE_RESERVE_CU_0 0x1f7c diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h index d7a17bae2584..e4ecd6c2d20e 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h @@ -47907,6 +47907,10 @@ // addressBlock: sqind +//SQ_DEBUG +#define SQ_DEBUG__SINGLE_MEMOP_MASK 0x00000001L +#define SQ_DEBUG__SINGLE_MEMOP__SHIFT 0x00000000 + //SQ_DEBUG_STS_GLOBAL #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h index 4f08f90856fc..3088a4a13cb5 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h @@ -17216,11 +17216,15 @@ #define SPI_GDBG_PER_VMID_CNTL__TRAP_EN__SHIFT 0x3 #define SPI_GDBG_PER_VMID_CNTL__EXCP_EN__SHIFT 0x4 #define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE__SHIFT 0xd +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START__SHIFT 0xe +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END__SHIFT 0xf #define SPI_GDBG_PER_VMID_CNTL__STALL_VMID_MASK 0x00000001L #define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE_MASK 0x00000006L #define SPI_GDBG_PER_VMID_CNTL__TRAP_EN_MASK 0x00000008L #define SPI_GDBG_PER_VMID_CNTL__EXCP_EN_MASK 0x00001FF0L #define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE_MASK 0x00002000L +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START_MASK 0x00004000L +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END_MASK 0x00008000L //SPI_COMPUTE_QUEUE_RESET #define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h index 3100de8b3881..393963502b7a 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h @@ -705,6 +705,46 @@ #define regSQC_ICACHE_UTCL1_STATUS_BASE_IDX 0 #define regSQC_DCACHE_UTCL1_STATUS 0x03d8 #define regSQC_DCACHE_UTCL1_STATUS_BASE_IDX 0 +#define regSQC_UE_EDC_LO 0x03d9 +#define regSQC_UE_EDC_LO_BASE_IDX 0 +#define regSQC_UE_EDC_HI 0x03da +#define regSQC_UE_EDC_HI_BASE_IDX 0 +#define regSQC_CE_EDC_LO 0x03db +#define regSQC_CE_EDC_LO_BASE_IDX 0 +#define regSQC_CE_EDC_HI 0x03dc +#define regSQC_CE_EDC_HI_BASE_IDX 0 +#define regSQ_UE_ERR_STATUS_LO 0x03dd +#define regSQ_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regSQ_UE_ERR_STATUS_HI 0x03de +#define regSQ_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regSQ_CE_ERR_STATUS_LO 0x03df +#define regSQ_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regSQ_CE_ERR_STATUS_HI 0x03e0 +#define regSQ_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regLDS_UE_ERR_STATUS_LO 0x03e1 +#define regLDS_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regLDS_UE_ERR_STATUS_HI 0x03e2 +#define regLDS_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regLDS_CE_ERR_STATUS_LO 0x03e3 +#define regLDS_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regLDS_CE_ERR_STATUS_HI 0x03e4 +#define regLDS_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regSP0_UE_ERR_STATUS_LO 0x03e5 +#define regSP0_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regSP0_UE_ERR_STATUS_HI 0x03e6 +#define regSP0_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regSP0_CE_ERR_STATUS_LO 0x03e7 +#define regSP0_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regSP0_CE_ERR_STATUS_HI 0x03e8 +#define regSP0_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regSP1_UE_ERR_STATUS_LO 0x03e9 +#define regSP1_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regSP1_UE_ERR_STATUS_HI 0x03ea +#define regSP1_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regSP1_CE_ERR_STATUS_LO 0x03eb +#define regSP1_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regSP1_CE_ERR_STATUS_HI 0x03ec +#define regSP1_CE_ERR_STATUS_HI_BASE_IDX 0 // addressBlock: xcd0_gc_shsdec @@ -727,6 +767,14 @@ #define regSPI_DSM_CNTL2_BASE_IDX 0 #define regSPI_EDC_CNT 0x0445 #define regSPI_EDC_CNT_BASE_IDX 0 +#define regSPI_UE_ERR_STATUS_LO 0x0446 +#define regSPI_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regSPI_UE_ERR_STATUS_HI 0x0447 +#define regSPI_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regSPI_CE_ERR_STATUS_LO 0x0448 +#define regSPI_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regSPI_CE_ERR_STATUS_HI 0x0449 +#define regSPI_CE_ERR_STATUS_HI_BASE_IDX 0 #define regSPI_DEBUG_BUSY 0x0450 #define regSPI_DEBUG_BUSY_BASE_IDX 0 #define regSPI_CONFIG_PS_CU_EN 0x0452 @@ -871,6 +919,14 @@ #define regTD_STATUS_BASE_IDX 0 #define regTD_POWER_CNTL 0x052a #define regTD_POWER_CNTL_BASE_IDX 0 +#define regTD_UE_EDC_LO 0x052b +#define regTD_UE_EDC_LO_BASE_IDX 0 +#define regTD_UE_EDC_HI 0x052c +#define regTD_UE_EDC_HI_BASE_IDX 0 +#define regTD_CE_EDC_LO 0x052d +#define regTD_CE_EDC_LO_BASE_IDX 0 +#define regTD_CE_EDC_HI 0x052e +#define regTD_CE_EDC_HI_BASE_IDX 0 #define regTD_DSM_CNTL 0x052f #define regTD_DSM_CNTL_BASE_IDX 0 #define regTD_DSM_CNTL2 0x0530 @@ -893,6 +949,14 @@ #define regTA_DSM_CNTL_BASE_IDX 0 #define regTA_DSM_CNTL2 0x0585 #define regTA_DSM_CNTL2_BASE_IDX 0 +#define regTA_UE_EDC_LO 0x0587 +#define regTA_UE_EDC_LO_BASE_IDX 0 +#define regTA_UE_EDC_HI 0x0588 +#define regTA_UE_EDC_HI_BASE_IDX 0 +#define regTA_CE_EDC_LO 0x0589 +#define regTA_CE_EDC_LO_BASE_IDX 0 +#define regTA_CE_EDC_HI 0x058a +#define regTA_CE_EDC_HI_BASE_IDX 0 // addressBlock: xcd0_gc_gdsdec @@ -923,6 +987,14 @@ #define regGDS_DSM_CNTL2_BASE_IDX 0 #define regGDS_WD_GDS_CSB 0x05ce #define regGDS_WD_GDS_CSB_BASE_IDX 0 +#define regGDS_UE_ERR_STATUS_LO 0x05cf +#define regGDS_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regGDS_UE_ERR_STATUS_HI 0x05d0 +#define regGDS_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regGDS_CE_ERR_STATUS_LO 0x05d1 +#define regGDS_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regGDS_CE_ERR_STATUS_HI 0x05d2 +#define regGDS_CE_ERR_STATUS_HI_BASE_IDX 0 // addressBlock: xcd0_gc_rbdec @@ -1243,6 +1315,10 @@ #define regGCEA_MAM_CTRL_BASE_IDX 0 #define regGCEA_MAM_CTRL2 0x0702 #define regGCEA_MAM_CTRL2_BASE_IDX 0 +#define regGCEA_UE_ERR_STATUS_LO 0x0706 +#define regGCEA_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regGCEA_UE_ERR_STATUS_HI 0x0707 +#define regGCEA_UE_ERR_STATUS_HI_BASE_IDX 0 #define regGCEA_DSM_CNTL 0x0708 #define regGCEA_DSM_CNTL_BASE_IDX 0 #define regGCEA_DSM_CNTLA 0x0709 @@ -1277,6 +1353,10 @@ #define regGCEA_SDP_BACKDOOR_DATACREDITS1_BASE_IDX 0 #define regGCEA_SDP_BACKDOOR_MISCCREDITS 0x0719 #define regGCEA_SDP_BACKDOOR_MISCCREDITS_BASE_IDX 0 +#define regGCEA_CE_ERR_STATUS_LO 0x071b +#define regGCEA_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regGCEA_CE_ERR_STATUS_HI 0x071d +#define regGCEA_CE_ERR_STATUS_HI_BASE_IDX 0 #define regGCEA_SDP_ENABLE 0x071f #define regGCEA_SDP_ENABLE_BASE_IDX 0 @@ -1389,6 +1469,14 @@ #define regATC_L2_CNTL4_BASE_IDX 0 #define regATC_L2_MM_GROUP_RT_CLASSES 0x0816 #define regATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 +#define regATC_L2_UE_ERR_STATUS_LO 0x081a +#define regATC_L2_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regATC_L2_UE_ERR_STATUS_HI 0x081b +#define regATC_L2_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regATC_L2_CE_ERR_STATUS_LO 0x081c +#define regATC_L2_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regATC_L2_CE_ERR_STATUS_HI 0x081d +#define regATC_L2_CE_ERR_STATUS_HI_BASE_IDX 0 // addressBlock: xcd0_gc_utcl2_vml2pfdec @@ -1475,6 +1563,30 @@ #define regUTCL2_EDC_MODE_BASE_IDX 0 #define regUTCL2_EDC_CONFIG 0x084c #define regUTCL2_EDC_CONFIG_BASE_IDX 0 +#define regVML2_UE_ERR_STATUS_LO 0x084d +#define regVML2_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regVML2_WALKER_UE_ERR_STATUS_LO 0x084e +#define regVML2_WALKER_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regUTCL2_UE_ERR_STATUS_LO 0x084f +#define regUTCL2_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regVML2_UE_ERR_STATUS_HI 0x0850 +#define regVML2_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regVML2_WALKER_UE_ERR_STATUS_HI 0x0851 +#define regVML2_WALKER_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regUTCL2_UE_ERR_STATUS_HI 0x0852 +#define regUTCL2_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regVML2_CE_ERR_STATUS_LO 0x0853 +#define regVML2_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regVML2_WALKER_CE_ERR_STATUS_LO 0x0854 +#define regVML2_WALKER_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regUTCL2_CE_ERR_STATUS_LO 0x0855 +#define regUTCL2_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regVML2_CE_ERR_STATUS_HI 0x0856 +#define regVML2_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regVML2_WALKER_CE_ERR_STATUS_HI 0x0857 +#define regVML2_WALKER_CE_ERR_STATUS_HI_BASE_IDX 0 +#define regUTCL2_CE_ERR_STATUS_HI 0x0858 +#define regUTCL2_CE_ERR_STATUS_HI_BASE_IDX 0 // addressBlock: xcd0_gc_utcl2_vml2vcdec @@ -2011,6 +2123,22 @@ #define regTC_CFG_L1_VOLATILE_BASE_IDX 0 #define regTC_CFG_L2_VOLATILE |