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| author | Kenneth Feng <kenneth.feng@amd.com> | 2024-05-16 09:05:17 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-05-20 16:20:26 -0400 |
| commit | e7d1f1162bb1de369be3a51ca6346bd862b6cc1c (patch) | |
| tree | f2463221f65220189814f569029a6c73ab11984d /drivers/gpu/drm/amd/include | |
| parent | 64af3d3d66c741c5cf6a62606ae37834973a2428 (diff) | |
| download | linux-e7d1f1162bb1de369be3a51ca6346bd862b6cc1c.tar.gz linux-e7d1f1162bb1de369be3a51ca6346bd862b6cc1c.tar.bz2 linux-e7d1f1162bb1de369be3a51ca6346bd862b6cc1c.zip | |
drm/amd/amdgpu: add thm 14.0.2 header file
add thm 14.0.2 header file
v2: add license, update to latest changes (Alex)
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_offset.h | 228 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_sh_mask.h | 940 |
2 files changed, 1168 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_offset.h new file mode 100644 index 000000000000..78a71b124d22 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_offset.h @@ -0,0 +1,228 @@ +/* + * Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * + */ +#ifndef _thm_14_0_2_OFFSET_HEADER +#define _thm_14_0_2_OFFSET_HEADER + + + +// addressBlock: thm_thm_SmuThmDec +// base address: 0x59800 +#define regTHM_TCON_CUR_TMP 0x0000 +#define regTHM_TCON_CUR_TMP_BASE_IDX 0 +#define regTHM_TCON_HTC 0x0001 +#define regTHM_TCON_HTC_BASE_IDX 0 +#define regTHM_TCON_THERM_TRIP 0x0002 +#define regTHM_TCON_THERM_TRIP_BASE_IDX 0 +#define regTHM_CTF_DELAY 0x0003 +#define regTHM_CTF_DELAY_BASE_IDX 0 +#define regTHM_GPIO_PROCHOT_CTRL 0x0004 +#define regTHM_GPIO_PROCHOT_CTRL_BASE_IDX 0 +#define regTHM_GPIO_THERMTRIP_CTRL 0x0005 +#define regTHM_GPIO_THERMTRIP_CTRL_BASE_IDX 0 +#define regTHM_GPIO_PWM_CTRL 0x0006 +#define regTHM_GPIO_PWM_CTRL_BASE_IDX 0 +#define regTHM_GPIO_TACHIN_CTRL 0x0007 +#define regTHM_GPIO_TACHIN_CTRL_BASE_IDX 0 +#define regTHM_GPIO_PUMPOUT_CTRL 0x0008 +#define regTHM_GPIO_PUMPOUT_CTRL_BASE_IDX 0 +#define regTHM_GPIO_PUMPIN_CTRL 0x0009 +#define regTHM_GPIO_PUMPIN_CTRL_BASE_IDX 0 +#define regTHM_THERMAL_INT_ENA 0x000a +#define regTHM_THERMAL_INT_ENA_BASE_IDX 0 +#define regTHM_THERMAL_INT_CTRL 0x000b +#define regTHM_THERMAL_INT_CTRL_BASE_IDX 0 +#define regTHM_THERMAL_INT_STATUS 0x000c +#define regTHM_THERMAL_INT_STATUS_BASE_IDX 0 +#define regTHM_SW_TEMP 0x000d +#define regTHM_SW_TEMP_BASE_IDX 0 +#define regCG_MULT_THERMAL_CTRL 0x000e +#define regCG_MULT_THERMAL_CTRL_BASE_IDX 0 +#define regCG_MULT_THERMAL_STATUS 0x000f +#define regCG_MULT_THERMAL_STATUS_BASE_IDX 0 +#define regCG_THERMAL_RANGE 0x0010 +#define regCG_THERMAL_RANGE_BASE_IDX 0 +#define regCG_FDO_CTRL0 0x0011 +#define regCG_FDO_CTRL0_BASE_IDX 0 +#define regCG_FDO_CTRL1 0x0012 +#define regCG_FDO_CTRL1_BASE_IDX 0 +#define regCG_FDO_CTRL2 0x0013 +#define regCG_FDO_CTRL2_BASE_IDX 0 +#define regCG_TACH_CTRL 0x0014 +#define regCG_TACH_CTRL_BASE_IDX 0 +#define regCG_TACH_STATUS 0x0015 +#define regCG_TACH_STATUS_BASE_IDX 0 +#define regCG_THERMAL_STATUS 0x0016 +#define regCG_THERMAL_STATUS_BASE_IDX 0 +#define regCG_PUMP_CTRL0 0x0017 +#define regCG_PUMP_CTRL0_BASE_IDX 0 +#define regCG_PUMP_CTRL1 0x0018 +#define regCG_PUMP_CTRL1_BASE_IDX 0 +#define regCG_PUMP_CTRL2 0x0019 +#define regCG_PUMP_CTRL2_BASE_IDX 0 +#define regCG_PUMP_TACH_CTRL 0x001a +#define regCG_PUMP_TACH_CTRL_BASE_IDX 0 +#define regCG_PUMP_TACH_STATUS 0x001b +#define regCG_PUMP_TACH_STATUS_BASE_IDX 0 +#define regCG_PUMP_STATUS 0x001c +#define regCG_PUMP_STATUS_BASE_IDX 0 +#define regTHM_TCON_LOCAL2 0x001d +#define regTHM_TCON_LOCAL2_BASE_IDX 0 +#define regTHM_TCON_LOCAL3 0x001e +#define regTHM_TCON_LOCAL3_BASE_IDX 0 +#define regTHM_TCON_LOCAL4 0x001f +#define regTHM_TCON_LOCAL4_BASE_IDX 0 +#define regTHM_TCON_LOCAL5 0x0020 +#define regTHM_TCON_LOCAL5_BASE_IDX 0 +#define regTHM_TCON_LOCAL6 0x0021 +#define regTHM_TCON_LOCAL6_BASE_IDX 0 +#define regTHM_TCON_LOCAL7 0x0022 +#define regTHM_TCON_LOCAL7_BASE_IDX 0 +#define regTHM_TCON_LOCAL8 0x0023 +#define regTHM_TCON_LOCAL8_BASE_IDX 0 +#define regTHM_TCON_LOCAL9 0x0024 +#define regTHM_TCON_LOCAL9_BASE_IDX 0 +#define regTHM_TCON_LOCAL10 0x0025 +#define regTHM_TCON_LOCAL10_BASE_IDX 0 +#define regTHM_TCON_LOCAL11 0x0026 +#define regTHM_TCON_LOCAL11_BASE_IDX 0 +#define regTHM_TCON_LOCAL12 0x0027 +#define regTHM_TCON_LOCAL12_BASE_IDX 0 +#define regTHM_TCON_LOCAL13 0x0028 +#define regTHM_TCON_LOCAL13_BASE_IDX 0 +#define regTHM_TCON_LOCAL14 0x0029 +#define regTHM_TCON_LOCAL14_BASE_IDX 0 +#define regTHM_TCON_LOCAL15 0x002a +#define regTHM_TCON_LOCAL15_BASE_IDX 0 +#define regTHM_BACO_CNTL 0x002d +#define regTHM_BACO_CNTL_BASE_IDX 0 +#define regTHM_BACO_TIMING0 0x002e +#define regTHM_BACO_TIMING0_BASE_IDX 0 +#define regTHM_BACO_TIMING1 0x002f +#define regTHM_BACO_TIMING1_BASE_IDX 0 +#define regTHM_BACO_TIMING2 0x0030 +#define regTHM_BACO_TIMING2_BASE_IDX 0 +#define regTHM_BACO_TIMING 0x0031 +#define regTHM_BACO_TIMING_BASE_IDX 0 +#define regXTAL_CNTL 0x0032 +#define regXTAL_CNTL_BASE_IDX 0 +#define regTHM_PWRMGT 0x0033 +#define regTHM_PWRMGT_BASE_IDX 0 +#define regSMUSBI_SBIREGADDR 0x0158 +#define regSMUSBI_SBIREGADDR_BASE_IDX 0 +#define regSMUSBI_SBIREGDATA 0x0159 +#define regSMUSBI_SBIREGDATA_BASE_IDX 0 +#define regSMUSBI_ERRATA_STAT_REG 0x015d +#define regSMUSBI_ERRATA_STAT_REG_BASE_IDX 0 +#define regSMUSBI_SBICTRL 0x015e +#define regSMUSBI_SBICTRL_BASE_IDX 0 +#define regSMUSBI_CKNBIRESET 0x015f +#define regSMUSBI_CKNBIRESET_BASE_IDX 0 +#define regSMUSBI_TIMING 0x0160 +#define regSMUSBI_TIMING_BASE_IDX 0 +#define regSMUSBI_HS_TIMING 0x0161 +#define regSMUSBI_HS_TIMING_BASE_IDX 0 +#define regSBTSI_REMOTE_TEMP 0x0162 +#define regSBTSI_REMOTE_TEMP_BASE_IDX 0 +#define regSBRMI_CONTROL 0x0163 +#define regSBRMI_CONTROL_BASE_IDX 0 +#define regSBRMI_COMMAND 0x0164 +#define regSBRMI_COMMAND_BASE_IDX 0 +#define regSBRMI_WRITE_DATA0 0x0166 +#define regSBRMI_WRITE_DATA0_BASE_IDX 0 +#define regSBRMI_WRITE_DATA1 0x0167 +#define regSBRMI_WRITE_DATA1_BASE_IDX 0 +#define regSBRMI_WRITE_DATA2 0x0168 +#define regSBRMI_WRITE_DATA2_BASE_IDX 0 +#define regSBRMI_READ_DATA0 0x016a +#define regSBRMI_READ_DATA0_BASE_IDX 0 +#define regSBRMI_READ_DATA1 0x016b +#define regSBRMI_READ_DATA1_BASE_IDX 0 +#define regSBRMI_CORE_EN_NUMBER 0x016c +#define regSBRMI_CORE_EN_NUMBER_BASE_IDX 0 +#define regSBRMI_CORE_EN_STATUS0 0x016d +#define regSBRMI_CORE_EN_STATUS0_BASE_IDX 0 +#define regSBRMI_CORE_EN_STATUS1 0x016e +#define regSBRMI_CORE_EN_STATUS1_BASE_IDX 0 +#define regSBRMI_APIC_STATUS0 0x016f +#define regSBRMI_APIC_STATUS0_BASE_IDX 0 +#define regSBRMI_APIC_STATUS1 0x0170 +#define regSBRMI_APIC_STATUS1_BASE_IDX 0 +#define regSBRMI_MCE_STATUS0 0x0171 +#define regSBRMI_MCE_STATUS0_BASE_IDX 0 +#define regSBRMI_MCE_STATUS1 0x0172 +#define regSBRMI_MCE_STATUS1_BASE_IDX 0 +#define regSMBUS_CNTL0 0x0173 +#define regSMBUS_CNTL0_BASE_IDX 0 +#define regSMBUS_CNTL1 0x0174 +#define regSMBUS_CNTL1_BASE_IDX 0 +#define regSMBUS_BLKWR_CMD_CTRL0 0x0175 +#define regSMBUS_BLKWR_CMD_CTRL0_BASE_IDX 0 +#define regSMBUS_BLKWR_CMD_CTRL1 0x0176 +#define regSMBUS_BLKWR_CMD_CTRL1_BASE_IDX 0 +#define regSMBUS_BLKRD_CMD_CTRL0 0x0177 +#define regSMBUS_BLKRD_CMD_CTRL0_BASE_IDX 0 +#define regSMBUS_BLKRD_CMD_CTRL1 0x0178 +#define regSMBUS_BLKRD_CMD_CTRL1_BASE_IDX 0 +#define regSMBUS_TIMING_CNTL0 0x0179 +#define regSMBUS_TIMING_CNTL0_BASE_IDX 0 +#define regSMBUS_TIMING_CNTL1 0x017a +#define regSMBUS_TIMING_CNTL1_BASE_IDX 0 +#define regSMBUS_TIMING_CNTL2 0x017b +#define regSMBUS_TIMING_CNTL2_BASE_IDX 0 +#define regSMBUS_TRIGGER_CNTL 0x017c +#define regSMBUS_TRIGGER_CNTL_BASE_IDX 0 +#define regSMBUS_UDID_CNTL0 0x017d +#define regSMBUS_UDID_CNTL0_BASE_IDX 0 +#define regSMBUS_UDID_CNTL1 0x017e +#define regSMBUS_UDID_CNTL1_BASE_IDX 0 +#define regSMBUS_UDID_CNTL2 0x017f +#define regSMBUS_UDID_CNTL2_BASE_IDX 0 +#define regSMUSBI_SMBUS 0x0180 +#define regSMUSBI_SMBUS_BASE_IDX 0 +#define regSMUSBI_ALERT 0x0181 +#define regSMUSBI_ALERT_BASE_IDX 0 +#define regSMBUS_BACO_DUMMY 0x0182 +#define regSMBUS_BACO_DUMMY_BASE_IDX 0 +#define regSMBUS_BACO_ADDR_RANGE0_LOW 0x0183 +#define regSMBUS_BACO_ADDR_RANGE0_LOW_BASE_IDX 0 +#define regSMBUS_BACO_ADDR_RANGE0_HIGH 0x0184 +#define regSMBUS_BACO_ADDR_RANGE0_HIGH_BASE_IDX 0 +#define regSMBUS_BACO_ADDR_RANGE1_LOW 0x0185 +#define regSMBUS_BACO_ADDR_RANGE1_LOW_BASE_IDX 0 +#define regSMBUS_BACO_ADDR_RANGE1_HIGH 0x0186 +#define regSMBUS_BACO_ADDR_RANGE1_HIGH_BASE_IDX 0 +#define regSMBUS_BACO_ADDR_RANGE2_LOW 0x0187 +#define regSMBUS_BACO_ADDR_RANGE2_LOW_BASE_IDX 0 +#define regSMBUS_BACO_ADDR_RANGE2_HIGH 0x0188 +#define regSMBUS_BACO_ADDR_RANGE2_HIGH_BASE_IDX 0 +#define regSMBUS_BACO_ADDR_RANGE3_LOW 0x0189 +#define regSMBUS_BACO_ADDR_RANGE3_LOW_BASE_IDX 0 +#define regSMBUS_BACO_ADDR_RANGE3_HIGH 0x018a +#define regSMBUS_BACO_ADDR_RANGE3_HIGH_BASE_IDX 0 +#define regSMBUS_BACO_ADDR_RANGE4_LOW 0x018b +#define regSMBUS_BACO_ADDR_RANGE4_LOW_BASE_IDX 0 +#define regSMBUS_BACO_ADDR_RANGE4_HIGH 0x018c +#define regSMBUS_BACO_ADDR_RANGE4_HIGH_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_sh_mask.h new file mode 100644 index 000000000000..a888afda94d4 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_sh_mask.h @@ -0,0 +1,940 @@ +/* + * Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * + */ +#ifndef _thm_14_0_2_SH_MASK_HEADER +#define _thm_14_0_2_SH_MASK_HEADER + + +// addressBlock: thm_thm_SmuThmDec +//THM_TCON_CUR_TMP +#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0 +#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5 +#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7 +#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8 +#define THM_TCON_CUR_TMP__REMOTE_TJ_SEL__SHIFT 0xd +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10 +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12 +#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13 +#define THM_TCON_CUR_TMP__MCM_EN__SHIFT 0x14 +#define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT 0x15 +#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK 0x0000001FL +#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK 0x00000060L +#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK 0x00000080L +#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK 0x00001F00L +#define THM_TCON_CUR_TMP__REMOTE_TJ_SEL_MASK 0x00006000L +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK 0x00030000L +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK 0x00040000L +#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK 0x00080000L +#define THM_TCON_CUR_TMP__MCM_EN_MASK 0x00100000L +#define THM_TCON_CUR_TMP__CUR_TEMP_MASK 0xFFE00000L +//THM_TCON_HTC +#define THM_TCON_HTC__HTC_EN__SHIFT 0x0 +#define THM_TCON_HTC__EXTERNAL_PROCHOT__SHIFT 0x2 +#define THM_TCON_HTC__INTERNAL_PROCHOT__SHIFT 0x3 +#define THM_TCON_HTC__HTC_ACTIVE__SHIFT 0x4 +#define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT 0x5 +#define THM_TCON_HTC__HTC_DIAG__SHIFT 0x8 +#define THM_TCON_HTC__DIS_PROCHOT_PIN_OUT__SHIFT 0x9 +#define THM_TCON_HTC__HTC_TO_IH_EN__SHIFT 0xa +#define THM_TCON_HTC__PROCHOT_TO_IH_EN__SHIFT 0xb +#define THM_TCON_HTC__PROCHOT_EVENT_SRC__SHIFT 0xc +#define THM_TCON_HTC__DIS_PROCHOT_PIN_IN__SHIFT 0xf +#define THM_TCON_HTC__HTC_TMP_LMT__SHIFT 0x10 +#define THM_TCON_HTC__HTC_HYST_LMT__SHIFT 0x17 +#define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT 0x1b +#define THM_TCON_HTC__HTC_EN_MASK 0x00000001L +#define THM_TCON_HTC__EXTERNAL_PROCHOT_MASK 0x00000004L +#define THM_TCON_HTC__INTERNAL_PROCHOT_MASK 0x00000008L +#define THM_TCON_HTC__HTC_ACTIVE_MASK 0x00000010L +#define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK 0x00000020L +#define THM_TCON_HTC__HTC_DIAG_MASK 0x00000100L +#define THM_TCON_HTC__DIS_PROCHOT_PIN_OUT_MASK 0x00000200L +#define THM_TCON_HTC__HTC_TO_IH_EN_MASK 0x00000400L +#define THM_TCON_HTC__PROCHOT_TO_IH_EN_MASK 0x00000800L +#define THM_TCON_HTC__PROCHOT_EVENT_SRC_MASK 0x00007000L +#define THM_TCON_HTC__DIS_PROCHOT_PIN_IN_MASK 0x00008000L +#define THM_TCON_HTC__HTC_TMP_LMT_MASK 0x007F0000L +#define THM_TCON_HTC__HTC_HYST_LMT_MASK 0x07800000L +#define THM_TCON_HTC__HTC_SLEW_SEL_MASK 0x18000000L +//THM_TCON_THERM_TRIP +#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY__SHIFT 0x0 +#define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1 +#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED__SHIFT 0x2 +#define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3 +#define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4 +#define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5 +#define THM_TCON_THERM_TRIP__THERM_TP_LMT__SHIFT 0x6 +#define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f +#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY_MASK 0x00000001L +#define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x00000002L +#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED_MASK 0x00000004L +#define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x00000008L +#define THM_TCON_THERM_TRIP__RSVD2_MASK 0x00000010L +#define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x00000020L +#define THM_TCON_THERM_TRIP__THERM_TP_LMT_MASK 0x00003FC0L +#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000L +//THM_CTF_DELAY +#define THM_CTF_DELAY__CTF_DELAY_CNT__SHIFT 0x0 +#define THM_CTF_DELAY__CTF_DELAY_CNT_MASK 0x000FFFFFL +//THM_GPIO_PROCHOT_CTRL +#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL__SHIFT 0x0 +#define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1 +#define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2 +#define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT 0x3 +#define THM_GPIO_PROCHOT_CTRL__S0__SHIFT 0x4 +#define THM_GPIO_PROCHOT_CTRL__S1__SHIFT 0x5 +#define THM_GPIO_PROCHOT_CTRL__RXEN__SHIFT 0x6 +#define THM_GPIO_PROCHOT_CTRL__RXSEL0__SHIFT 0x7 +#define THM_GPIO_PROCHOT_CTRL__RXSEL1__SHIFT 0x8 +#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT 0x10 +#define THM_GPIO_PROCHOT_CTRL__OE__SHIFT 0x11 +#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT 0x12 +#define THM_GPIO_PROCHOT_CTRL__A__SHIFT 0x13 +#define THM_GPIO_PROCHOT_CTRL__Y__SHIFT 0x1f +#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL_MASK 0x00000001L +#define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x00000002L +#define THM_GPIO_PROCHOT_CTRL__PU_MASK 0x00000004L +#define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK 0x00000008L +#define THM_GPIO_PROCHOT_CTRL__S0_MASK 0x00000010L +#define THM_GPIO_PROCHOT_CTRL__S1_MASK 0x00000020L +#define THM_GPIO_PROCHOT_CTRL__RXEN_MASK 0x00000040L +#define THM_GPIO_PROCHOT_CTRL__RXSEL0_MASK 0x00000080L +#define THM_GPIO_PROCHOT_CTRL__RXSEL1_MASK 0x00000100L +#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK 0x00010000L +#define THM_GPIO_PROCHOT_CTRL__OE_MASK 0x00020000L +#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK 0x00040000L +#define THM_GPIO_PROCHOT_CTRL__A_MASK 0x00080000L +#define THM_GPIO_PROCHOT_CTRL__Y_MASK 0x80000000L +//THM_GPIO_THERMTRIP_CTRL +#define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL__SHIFT 0x0 +#define THM_GPIO_THERMTRIP_CTRL__PD__SHIFT 0x1 +#define THM_GPIO_THERMTRIP_CTRL__PU__SHIFT 0x2 +#define THM_GPIO_THERMTRIP_CTRL__SCHMEN__SHIFT 0x3 +#define THM_GPIO_THERMTRIP_CTRL__S0__SHIFT 0x4 +#define THM_GPIO_THERMTRIP_CTRL__S1__SHIFT 0x5 +#define THM_GPIO_THERMTRIP_CTRL__RXEN__SHIFT 0x6 +#define THM_GPIO_THERMTRIP_CTRL__RXSEL0__SHIFT 0x7 +#define THM_GPIO_THERMTRIP_CTRL__RXSEL1__SHIFT 0x8 +#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE__SHIFT 0x10 +#define THM_GPIO_THERMTRIP_CTRL__OE__SHIFT 0x11 +#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE__SHIFT 0x12 +#define THM_GPIO_THERMTRIP_CTRL__A__SHIFT 0x13 +#define THM_GPIO_THERMTRIP_CTRL__CTFEN__SHIFT 0x14 +#define THM_GPIO_THERMTRIP_CTRL__Y__SHIFT 0x1f +#define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL_MASK 0x00000001L +#define THM_GPIO_THERMTRIP_CTRL__PD_MASK 0x00000002L +#define THM_GPIO_THERMTRIP_CTRL__PU_MASK 0x00000004L +#define THM_GPIO_THERMTRIP_CTRL__SCHMEN_MASK 0x00000008L +#define THM_GPIO_THERMTRIP_CTRL__S0_MASK 0x00000010L +#define THM_GPIO_THERMTRIP_CTRL__S1_MASK 0x00000020L +#define THM_GPIO_THERMTRIP_CTRL__RXEN_MASK 0x00000040L +#define THM_GPIO_THERMTRIP_CTRL__RXSEL0_MASK 0x00000080L +#define THM_GPIO_THERMTRIP_CTRL__RXSEL1_MASK 0x00000100L +#define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE_MASK 0x00010000L +#define THM_GPIO_THERMTRIP_CTRL__OE_MASK 0x00020000L +#define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE_MASK 0x00040000L +#define THM_GPIO_THERMTRIP_CTRL__A_MASK 0x00080000L +#define THM_GPIO_THERMTRIP_CTRL__CTFEN_MASK 0x00100000L +#define THM_GPIO_THERMTRIP_CTRL__Y_MASK 0x80000000L +//THM_GPIO_PWM_CTRL +#define THM_GPIO_PWM_CTRL__TXIMPSEL__SHIFT 0x0 +#define THM_GPIO_PWM_CTRL__PD__SHIFT 0x1 +#define THM_GPIO_PWM_CTRL__PU__SHIFT 0x2 +#define THM_GPIO_PWM_CTRL__SCHMEN__SHIFT 0x3 +#define THM_GPIO_PWM_CTRL__S0__SHIFT 0x4 +#define THM_GPIO_PWM_CTRL__S1__SHIFT 0x5 +#define THM_GPIO_PWM_CTRL__RXEN__SHIFT 0x6 +#define THM_GPIO_PWM_CTRL__RXSEL0__SHIFT 0x7 +#define THM_GPIO_PWM_CTRL__RXSEL1__SHIFT 0x8 +#define THM_GPIO_PWM_CTRL__OE_OVERRIDE__SHIFT 0x10 +#define THM_GPIO_PWM_CTRL__OE__SHIFT 0x11 +#define THM_GPIO_PWM_CTRL__A_OVERRIDE__SHIFT 0x12 +#define THM_GPIO_PWM_CTRL__A__SHIFT 0x13 +#define THM_GPIO_PWM_CTRL__Y__SHIFT 0x1f +#define THM_GPIO_PWM_CTRL__TXIMPSEL_MASK 0x00000001L +#define THM_GPIO_PWM_CTRL__PD_MASK 0x00000002L +#define THM_GPIO_PWM_CTRL__PU_MASK 0x00000004L +#define THM_GPIO_PWM_CTRL__SCHMEN_MASK 0x00000008L +#define THM_GPIO_PWM_CTRL__S0_MASK 0x00000010L +#define THM_GPIO_PWM_CTRL__S1_MASK 0x00000020L +#define THM_GPIO_PWM_CTRL__RXEN_MASK 0x00000040L +#define THM_GPIO_PWM_CTRL__RXSEL0_MASK 0x00000080L +#define THM_GPIO_PWM_CTRL__RXSEL1_MASK 0x00000100L +#define THM_GPIO_PWM_CTRL__OE_OVERRIDE_MASK 0x00010000L +#define THM_GPIO_PWM_CTRL__OE_MASK 0x00020000L +#define THM_GPIO_PWM_CTRL__A_OVERRIDE_MASK 0x00040000L +#define THM_GPIO_PWM_CTRL__A_MASK 0x00080000L +#define THM_GPIO_PWM_CTRL__Y_MASK 0x80000000L +//THM_GPIO_TACHIN_CTRL +#define THM_GPIO_TACHIN_CTRL__TXIMPSEL__SHIFT 0x0 +#define THM_GPIO_TACHIN_CTRL__PD__SHIFT 0x1 +#define THM_GPIO_TACHIN_CTRL__PU__SHIFT 0x2 +#define THM_GPIO_TACHIN_CTRL__SCHMEN__SHIFT 0x3 +#define THM_GPIO_TACHIN_CTRL__S0__SHIFT 0x4 +#define THM_GPIO_TACHIN_CTRL__S1__SHIFT 0x5 +#define THM_GPIO_TACHIN_CTRL__RXEN__SHIFT 0x6 +#define THM_GPIO_TACHIN_CTRL__RXSEL0__SHIFT 0x7 +#define THM_GPIO_TACHIN_CTRL__RXSEL1__SHIFT 0x8 +#define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE__SHIFT 0x10 +#define THM_GPIO_TACHIN_CTRL__OE__SHIFT 0x11 +#define THM_GPIO_TACHIN_CTRL__A_OVERRIDE__SHIFT 0x12 +#define THM_GPIO_TACHIN_CTRL__A__SHIFT 0x13 +#define THM_GPIO_TACHIN_CTRL__Y__SHIFT 0x1f +#define THM_GPIO_TACHIN_CTRL__TXIMPSEL_MASK 0x00000001L +#define THM_GPIO_TACHIN_CTRL__PD_MASK 0x00000002L +#define THM_GPIO_TACHIN_CTRL__PU_MASK 0x00000004L +#define THM_GPIO_TACHIN_CTRL__SCHMEN_MASK 0x00000008L +#define THM_GPIO_TACHIN_CTRL__S0_MASK 0x00000010L +#define THM_GPIO_TACHIN_CTRL__S1_MASK 0x00000020L +#define THM_GPIO_TACHIN_CTRL__RXEN_MASK 0x00000040L +#define THM_GPIO_TACHIN_CTRL__RXSEL0_MASK 0x00000080L +#define THM_GPIO_TACHIN_CTRL__RXSEL1_MASK 0x00000100L +#define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE_MASK 0x00010000L +#define THM_GPIO_TACHIN_CTRL__OE_MASK 0x00020000L +#define THM_GPIO_TACHIN_CTRL__A_OVERRIDE_MASK 0x00040000L +#define THM_GPIO_TACHIN_CTRL__A_MASK 0x00080000L +#define THM_GPIO_TACHIN_CTRL__Y_MASK |