drm/amdgpu: Add soc24 chip enum definitions (v4)

Add enum definitions for soc24.

v2: Updates (Alex)
v3: Updates (Alex)
v4: Fix clash with display code (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 21073 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/include/soc24_enum.h b/drivers/gpu/drm/amd/include/soc24_enum.h
new file mode 100644
index 000000000000..c47b8cc2f203
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/soc24_enum.h
@@ -0,0 +1,21073 @@
+/*
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#if !defined (_soc24_ENUM_HEADER)
+#define _soc24_ENUM_HEADER
+
+#ifndef _DRIVER_BUILD
+#ifndef GL_ZERO
+#define GL__ZERO                      BLEND_ZERO
+#define GL__ONE                       BLEND_ONE
+#define GL__SRC_COLOR                 BLEND_SRC_COLOR
+#define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
+#define GL__DST_COLOR                 BLEND_DST_COLOR
+#define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
+#define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
+#define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
+#define GL__DST_ALPHA                 BLEND_DST_ALPHA
+#define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
+#define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
+#define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
+#define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
+#define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
+#define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
+#endif
+#endif
+
+
+/*
+ * CP_PERFMON_ENABLE_MODE enum
+ */
+
+typedef enum CP_PERFMON_ENABLE_MODE {
+CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT      = 0x00000000,
+CP_PERFMON_ENABLE_MODE_RESERVED_1        = 0x00000001,
+CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002,
+CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003,
+} CP_PERFMON_ENABLE_MODE;
+
+/*
+ * CP_PERFMON_STATE enum
+ */
+
+typedef enum CP_PERFMON_STATE {
+CP_PERFMON_STATE_DISABLE_AND_RESET       = 0x00000000,
+CP_PERFMON_STATE_START_COUNTING          = 0x00000001,
+CP_PERFMON_STATE_STOP_COUNTING           = 0x00000002,
+CP_PERFMON_STATE_RESERVED_3              = 0x00000003,
+CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
+CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM  = 0x00000005,
+} CP_PERFMON_STATE;
+
+/*
+ * ENUM_NUM_SIMD_PER_CU enum
+ */
+
+typedef enum ENUM_NUM_SIMD_PER_CU {
+NUM_SIMD_PER_CU                          = 0x00000004,
+} ENUM_NUM_SIMD_PER_CU;
+
+/*
+ * GATCL1RequestType enum
+ */
+
+typedef enum GATCL1RequestType {
+GATCL1_TYPE_NORMAL                       = 0x00000000,
+GATCL1_TYPE_SHOOTDOWN                    = 0x00000001,
+GATCL1_TYPE_BYPASS                       = 0x00000002,
+} GATCL1RequestType;
+
+/*
+ * GL0V_CACHE_POLICIES enum
+ */
+
+typedef enum GL0V_CACHE_POLICIES {
+GL0V_CACHE_POLICY_MISS_LRU               = 0x00000000,
+GL0V_CACHE_POLICY_MISS_EVICT             = 0x00000001,
+GL0V_CACHE_POLICY_HIT_LRU                = 0x00000002,
+GL0V_CACHE_POLICY_HIT_EVICT              = 0x00000003,
+GL0V_CACHE_POLICY_MISS_INVAL             = 0x00000004,
+} GL0V_CACHE_POLICIES;
+
+/*
+ * GL1_CACHE_POLICIES enum
+ */
+
+typedef enum GL1_CACHE_POLICIES {
+GL1_CACHE_POLICY_MISS_LRU                = 0x00000000,
+GL1_CACHE_POLICY_MISS_EVICT              = 0x00000001,
+GL1_CACHE_POLICY_HIT_LRU                 = 0x00000002,
+GL1_CACHE_POLICY_HIT_EVICT               = 0x00000003,
+} GL1_CACHE_POLICIES;
+
+/*
+ * GL1_CACHE_STORE_POLICIES enum
+ */
+
+typedef enum GL1_CACHE_STORE_POLICIES {
+GL1_CACHE_STORE_POLICY_BYPASS            = 0x00000000,
+} GL1_CACHE_STORE_POLICIES;
+
+/*
+ * GL2_CACHE_POLICIES enum
+ */
+
+typedef enum GL2_CACHE_POLICIES {
+GL2_CACHE_POLICY_LRU                     = 0x00000000,
+GL2_CACHE_POLICY_STREAM                  = 0x00000001,
+GL2_CACHE_POLICY_NOA                     = 0x00000002,
+GL2_CACHE_POLICY_BYPASS                  = 0x00000003,
+} GL2_CACHE_POLICIES;
+
+/*
+ * GL2_NACKS enum
+ */
+
+typedef enum GL2_NACKS {
+GL2_NACK_NO_FAULT                        = 0x00000000,
+GL2_NACK_PAGE_FAULT                      = 0x00000001,
+GL2_NACK_PROTECTION_FAULT                = 0x00000002,
+GL2_NACK_DATA_ERROR                      = 0x00000003,
+} GL2_NACKS;
+
+/*
+ * GL2_OP enum
+ */
+
+typedef enum GL2_OP {
+GL2_OP_READ                              = 0x00000000,
+GL2_OP_ATOMIC_FCMPSWAP_RTN_32            = 0x00000001,
+GL2_OP_ATOMIC_FMIN_RTN_32                = 0x00000002,
+GL2_OP_ATOMIC_FMAX_RTN_32                = 0x00000003,
+GL2_OP_ATOMIC_PK_ADD_FP16_RTN            = 0x00000004,
+GL2_OP_ATOMIC_FADD_RTN_32                = 0x00000005,
+GL2_OP_ATOMIC_PK_ADD_BF16_RTN            = 0x00000006,
+GL2_OP_ATOMIC_SWAP_RTN_32                = 0x00000007,
+GL2_OP_ATOMIC_CMPSWAP_RTN_32             = 0x00000008,
+GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009,
+GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32   = 0x0000000a,
+GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32   = 0x0000000b,
+GL2_OP_PROBE_FILTER                      = 0x0000000c,
+GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32   = 0x0000000d,
+GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e,
+GL2_OP_ATOMIC_ADD_RTN_32                 = 0x0000000f,
+GL2_OP_ATOMIC_SUB_RTN_32                 = 0x00000010,
+GL2_OP_ATOMIC_SMIN_RTN_32                = 0x00000011,
+GL2_OP_ATOMIC_UMIN_RTN_32                = 0x00000012,
+GL2_OP_ATOMIC_SMAX_RTN_32                = 0x00000013,
+GL2_OP_ATOMIC_UMAX_RTN_32                = 0x00000014,
+GL2_OP_ATOMIC_AND_RTN_32                 = 0x00000015,
+GL2_OP_ATOMIC_OR_RTN_32                  = 0x00000016,
+GL2_OP_ATOMIC_XOR_RTN_32                 = 0x00000017,
+GL2_OP_ATOMIC_INC_RTN_32                 = 0x00000018,
+GL2_OP_ATOMIC_DEC_RTN_32                 = 0x00000019,
+GL2_OP_ATOMIC_CLAMP_SUB_RTN_32           = 0x0000001a,
+GL2_OP_ATOMIC_COND_SUB_RTN_32            = 0x0000001b,
+GL2_OP_UTC_PROBE                         = 0x0000001d,
+GL2_OP_LOAD_RESERVE                      = 0x0000001e,
+GL2_OP_WRITE                             = 0x00000020,
+GL2_OP_ATOMIC_FCMPSWAP_RTN_64            = 0x00000021,
+GL2_OP_ATOMIC_FMIN_RTN_64                = 0x00000022,
+GL2_OP_ATOMIC_FMAX_RTN_64                = 0x00000023,
+GL2_OP_ATOMIC_SWAP_RTN_64                = 0x00000027,
+GL2_OP_ATOMIC_CMPSWAP_RTN_64             = 0x00000028,
+GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029,
+GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64   = 0x0000002a,
+GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64   = 0x0000002b,
+GL2_OP_ATOMIC_ADD_RTN_64                 = 0x0000002f,
+GL2_OP_ATOMIC_SUB_RTN_64                 = 0x00000030,
+GL2_OP_ATOMIC_SMIN_RTN_64                = 0x00000031,
+GL2_OP_ATOMIC_UMIN_RTN_64                = 0x00000032,
+GL2_OP_ATOMIC_SMAX_RTN_64                = 0x00000033,
+GL2_OP_ATOMIC_UMAX_RTN_64                = 0x00000034,
+GL2_OP_ATOMIC_AND_RTN_64                 = 0x00000035,
+GL2_OP_ATOMIC_OR_RTN_64                  = 0x00000036,
+GL2_OP_ATOMIC_XOR_RTN_64                 = 0x00000037,
+GL2_OP_ATOMIC_INC_RTN_64                 = 0x00000038,
+GL2_OP_ATOMIC_DEC_RTN_64                 = 0x00000039,
+GL2_OP_WRITE_ZERO_SIZE                   = 0x0000003b,
+GL2_OP_GL2_INV                           = 0x0000003d,
+GL2_OP_ATOMIC_STORE_COND_RTN             = 0x0000003e,
+GL2_OP_GL1_INV                           = 0x00000040,
+GL2_OP_ATOMIC_FCMPSWAP_32                = 0x00000041,
+GL2_OP_ATOMIC_FMIN_32                    = 0x00000042,
+GL2_OP_ATOMIC_FMAX_32                    = 0x00000043,
+GL2_OP_ATOMIC_PK_ADD_FP16                = 0x00000044,
+GL2_OP_ATOMIC_FADD_32                    = 0x00000045,
+GL2_OP_ATOMIC_PK_ADD_BF16                = 0x00000046,
+GL2_OP_ATOMIC_SWAP_32                    = 0x00000047,
+GL2_OP_ATOMIC_CMPSWAP_32                 = 0x00000048,
+GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32   = 0x00000049,
+GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32       = 0x0000004a,
+GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32       = 0x0000004b,
+GL2_OP_ATOMIC_UMIN_8                     = 0x0000004c,
+GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32       = 0x0000004d,
+GL2_OP_ATOMIC_ADD_32                     = 0x0000004f,
+GL2_OP_ATOMIC_SUB_32                     = 0x00000050,
+GL2_OP_ATOMIC_SMIN_32                    = 0x00000051,
+GL2_OP_ATOMIC_UMIN_32                    = 0x00000052,
+GL2_OP_ATOMIC_SMAX_32                    = 0x00000053,
+GL2_OP_ATOMIC_UMAX_32                    = 0x00000054,
+GL2_OP_ATOMIC_AND_32                     = 0x00000055,
+GL2_OP_ATOMIC_OR_32                      = 0x00000056,
+GL2_OP_ATOMIC_XOR_32                     = 0x00000057,
+GL2_OP_ATOMIC_INC_32                     = 0x00000058,
+GL2_OP_ATOMIC_DEC_32                     = 0x00000059,
+GL2_OP_NOP_RTN0                          = 0x0000005b,
+GL2_OP_GL2_WB                            = 0x0000005d,
+GL2_OP_FORCE_EXISTING_DATA_TO_DECOMPRESS = 0x0000005e,
+GL2_OP_ATOMIC_FCMPSWAP_64                = 0x00000061,
+GL2_OP_ATOMIC_FMIN_64                    = 0x00000062,
+GL2_OP_ATOMIC_FMAX_64                    = 0x00000063,
+GL2_OP_ATOMIC_SWAP_64                    = 0x00000067,
+GL2_OP_ATOMIC_CMPSWAP_64                 = 0x00000068,
+GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64   = 0x00000069,
+GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64       = 0x0000006a,
+GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64       = 0x0000006b,
+GL2_OP_ATOMIC_ADD_64                     = 0x0000006f,
+GL2_OP_ATOMIC_SUB_64                     = 0x00000070,
+GL2_OP_ATOMIC_SMIN_64                    = 0x00000071,
+GL2_OP_ATOMIC_UMIN_64                    = 0x00000072,
+GL2_OP_ATOMIC_SMAX_64                    = 0x00000073,
+GL2_OP_ATOMIC_UMAX_64                    = 0x00000074,
+GL2_OP_ATOMIC_AND_64                     = 0x00000075,
+GL2_OP_ATOMIC_OR_64                      = 0x00000076,
+GL2_OP_ATOMIC_XOR_64                     = 0x00000077,
+GL2_OP_ATOMIC_INC_64                     = 0x00000078,
+GL2_OP_ATOMIC_DEC_64                     = 0x00000079,
+GL2_OP_ATOMIC_UMAX_8                     = 0x0000007a,
+GL2_OP_NOP_ACK                           = 0x0000007b,
+GL2_OP_GL2_WBINV                         = 0x0000007d,
+GL2_OP_READ_COMPRESSION_KEY              = 0x0000007e,
+} GL2_OP;
+
+/*
+ * GL2_OP_MASKS enum
+ */
+
+typedef enum GL2_OP_MASKS {
+GL2_OP_MASK_FLUSH_DENROM                 = 0x00000008,
+GL2_OP_MASK_64                           = 0x00000020,
+GL2_OP_MASK_NO_RTN                       = 0x00000040,
+} GL2_OP_MASKS;
+
+/*
+ * Hdp_SurfaceEndian enum
+ */
+
+typedef enum Hdp_SurfaceEndian {
+HDP_ENDIAN_NONE                          = 0x00000000,
+HDP_ENDIAN_8IN16                         = 0x00000001,
+HDP_ENDIAN_8IN32                         = 0x00000002,
+HDP_ENDIAN_8IN64                         = 0x00000003,
+} Hdp_SurfaceEndian;
+
+/*
+ * MTYPE enum
+ */
+
+typedef enum MTYPE {
+MTYPE_C_RW_US                            = 0x00000000,
+MTYPE_RESERVED_1                         = 0x00000001,
+MTYPE_C_RO_S                             = 0x00000002,
+MTYPE_UC                                 = 0x00000003,
+MTYPE_C_RW_S                             = 0x00000004,
+MTYPE_RESERVED_5                         = 0x00000005,
+MTYPE_C_RO_US                            = 0x00000006,
+MTYPE_RESERVED_7                         = 0x00000007,
+} MTYPE;
+
+/*
+ * PERFMON_COUNTER_MODE enum
+ */
+
+typedef enum PERFMON_COUNTER_MODE {
+PERFMON_COUNTER_MODE_ACCUM               = 0x00000000,
+PERFMON_COUNTER_MODE_ACTIVE_CYCLES       = 0x00000001,
+PERFMON_COUNTER_MODE_MAX                 = 0x00000002,
+PERFMON_COUNTER_MODE_DIRTY               = 0x00000003,
+PERFMON_COUNTER_MODE_SAMPLE              = 0x00000004,
+PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005,
+PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006,
+PERFMON_COUNTER_MODE_CYCLES_GE_HI        = 0x00000007,
+PERFMON_COUNTER_MODE_CYCLES_EQ_HI        = 0x00000008,
+PERFMON_COUNTER_MODE_INACTIVE_CYCLES     = 0x00000009,
+PERFMON_COUNTER_MODE_RESERVED            = 0x0000000f,
+} PERFMON_COUNTER_MODE;
+
+/*
+ * PERFMON_SPM_MODE enum
+ */
+
+typedef enum PERFMON_SPM_MODE {
+PERFMON_SPM_MODE_OFF                     = 0x00000000,
+PERFMON_SPM_MODE_16BIT_CLAMP             = 0x00000001,
+PERFMON_SPM_MODE_16BIT_NO_CLAMP          = 0x00000002,
+PERFMON_SPM_MODE_32BIT_CLAMP             = 0x00000003,
+PERFMON_SPM_MODE_32BIT_NO_CLAMP          = 0x00000004,
+PERFMON_SPM_MODE_RESERVED_5              = 0x00000005,
+PERFMON_SPM_MODE_RESERVED_6              = 0x00000006,
+PERFMON_SPM_MODE_RESERVED_7              = 0x00000007,
+PERFMON_SPM_MODE_TEST_MODE_0             = 0x00000008,
+PERFMON_SPM_MODE_TEST_MODE_1             = 0x00000009,
+PERFMON_SPM_MODE_TEST_MODE_2             = 0x0000000a,
+} PERFMON_SPM_MODE;
+
+/*
+ * READ_COMPRESSION_MODE enum
+ */
+
+typedef enum READ_COMPRESSION_MODE {
+COMPRESSION_MODE_BYPASS_COMPRESSION      = 0x00000000,
+COMPRESSION_MODE_READ_RAW_COMPRESSED_DATA = 0x00000001,
+COMPRESSION_MODE_READ_DECOMPRESSED       = 0x00000002,
+} READ_COMPRESSION_MODE;
+
+/*
+ * ReadPolicy enum
+ */
+
+typedef enum ReadPolicy {
+CACHE_LRU_RD                             = 0x00000000,
+CACHE_STREAM_RD                          = 0x00000001,
+CACHE_NOA                                = 0x00000002,
+RESERVED_RDPOLICY                        = 0x00000003,
+} ReadPolicy;
+
+/*
+ * SCOPE enum
+ */
+
+typedef enum SCOPE {
+SCOPE_CU                                 = 0x00000000,
+SCOPE_SE                                 = 0x00000001,
+SCOPE_DEV                                = 0x00000002,
+SCOPE_SYS                                = 0x00000003,
+} SCOPE;
+
+/*
+ * SDMA_PERFMON_SEL enum
+ */
+
+typedef enum SDMA_PERFMON_SEL {
+SDMA_PERFMON_SEL_CYCLE                   = 0x00000000,
+SDMA_PERFMON_SEL_IDLE                    = 0x00000001,
+SDMA_PERFMON_SEL_REG_IDLE                = 0x00000002,
+SDMA_PERFMON_SEL_RB_EMPTY                = 0x00000003,
+SDMA_PERFMON_SEL_RB_FULL                 = 0x00000004,
+SDMA_PERFMON_SEL_RB_WPTR_WRAP            = 0x00000005,
+SDMA_PERFMON_SEL_RB_RPTR_WRAP            = 0x00000006,
+SDMA_PERFMON_SEL_RB_WPTR_POLL_READ       = 0x00000007,
+SDMA_PERFMON_SEL_RB_RPTR_WB              = 0x00000008,
+SDMA_PERFMON_SEL_RB_CMD_IDLE             = 0x00000009,
+SDMA_PERFMON_SEL_RB_CMD_FULL             = 0x0000000a,
+SDMA_PERFMON_SEL_IB_CMD_IDLE             = 0x0000000b,
+SDMA_PERFMON_SEL_IB_CMD_FULL             = 0x0000000c,
+SDMA_PERFMON_SEL_EX_IDLE                 = 0x0000000d,
+SDMA_PERFMON_SEL_SRBM_REG_SEND           = 0x0000000e,
+SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f,
+SDMA_PERFMON_SEL_WR_BA_RTR               = 0x00000010,
+SDMA_PERFMON_SEL_MC_WR_IDLE              = 0x00000011,
+SDMA_PERFMON_SEL_MC_WR_COUNT             = 0x00000012,
+SDMA_PERFMON_SEL_RD_BA_RTR               = 0x00000013,
+SDMA_PERFMON_SEL_MC_RD_IDLE              = 0x00000014,
+SDMA_PERFMON_SEL_MC_RD_COUNT             = 0x00000015,
+SDMA_PERFMON_SEL_MC_RD_RET_STALL         = 0x00000016,
+SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE      = 0x00000017,
+SDMA_PERFMON_SEL_SEM_IDLE                = 0x0000001a,
+SDMA_PERFMON_SEL_SEM_REQ_STALL           = 0x0000001b,
+SDMA_PERFMON_SEL_SEM_REQ_COUNT           = 0x0000001c,
+SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE     = 0x0000001d,
+SDMA_PERFMON_SEL_SEM_RESP_FAIL           = 0x0000001e,
+SDMA_PERFMON_SEL_SEM_RESP_PASS           = 0x0000001f,
+SDMA_PERFMON_SEL_INT_IDLE                = 0x00000020,
+SDMA_PERFMON_SEL_INT_REQ_STALL           = 0x00000021,
+SDMA_PERFMON_SEL_INT_REQ_COUNT           = 0x00000022,
+SDMA_PERFMON_SEL_INT_RESP_ACCEPTED       = 0x00000023,
+SDMA_PERFMON_SEL_INT_RESP_RETRY          = 0x00000024,
+SDMA_PERFMON_SEL_NUM_PACKET              = 0x00000025,
+SDMA_PERFMON_SEL_CE_WREQ_IDLE            = 0x00000027,
+SDMA_PERFMON_SEL_CE_WR_IDLE              = 0x00000028,
+SDMA_PERFMON_SEL_CE_SPLIT_IDLE           = 0x00000029,
+SDMA_PERFMON_SEL_CE_RREQ_IDLE            = 0x0000002a,
+SDMA_PERFMON_SEL_CE_OUT_IDLE             = 0x0000002b,
+SDMA_PERFMON_SEL_CE_IN_IDLE              = 0x0000002c,
+SDMA_PERFMON_SEL_CE_DST_IDLE             = 0x0000002d,
+SDMA_PERFMON_SEL_CE_AFIFO_FULL           = 0x00000030,
+SDMA_PERFMON_SEL_DUMMY_0                 = 0x00000031,
+SDMA_PERFMON_SEL_DUMMY_1                 = 0x00000032,
+SDMA_PERFMON_SEL_CE_INFO_FULL            = 0x00000033,
+SDMA_PERFMON_SEL_CE_INFO1_FULL           = 0x00000034,
+SDMA_PERFMON_SEL_CE_RD_STALL             = 0x00000035,
+SDMA_PERFMON_SEL_CE_WR_STALL             = 0x00000036,
+SDMA_PERFMON_SEL_QUEUE0_SELECT           = 0x00000037,
+SDMA_PERFMON_SEL_QUEUE1_SELECT           = 0x00000038,
+SDMA_PERFMON_SEL_QUEUE2_SELECT           = 0x00000039,
+SDMA_PERFMON_SEL_QUEUE3_SELECT           = 0x0000003a,
+SDMA_PERFMON_SEL_CTX_CHANGE              = 0x0000003b,
+SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED      = 0x0000003c,
+SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION    = 0x0000003d,
+SDMA_PERFMON_SEL_DOORBELL                = 0x0000003e,
+SDMA_PERFMON_SEL_MCU_L1_WR_VLD           = 0x0000003f,
+SDMA_PERFMON_SEL_CE_L1_WR_VLD            = 0x00000040,
+SDMA_PERFMON_SEL_CPF_SDMA_INVREQ         = 0x00000041,
+SDMA_PERFMON_SEL_SDMA_CPF_INVACK         = 0x00000042,
+SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ       = 0x00000043,
+SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK       = 0x00000044,
+SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL   = 0x00000045,
+SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL   = 0x00000046,
+SDMA_PERFMON_SEL_UTCL2_RET_XNACK         = 0x00000047,
+SDMA_PERFMON_SEL_UTCL2_RET_ACK           = 0x00000048,
+SDMA_PERFMON_SEL_UTCL2_FREE              = 0x00000049,
+SDMA_PERFMON_SEL_SDMA_UTCL2_SEND         = 0x0000004a,
+SDMA_PERFMON_SEL_DMA_L1_WR_SEND          = 0x0000004b,
+SDMA_PERFMON_SEL_DMA_L1_RD_SEND          = 0x0000004c,
+SDMA_PERFMON_SEL_DMA_MC_WR_SEND          = 0x0000004d,
+SDMA_PERFMON_SEL_DMA_MC_RD_SEND          = 0x0000004e,
+SDMA_PERFMON_SEL_GPUVM_INV_HIGH          = 0x0000004f,
+SDMA_PERFMON_SEL_GPUVM_INV_LOW           = 0x00000050,
+SDMA_PERFMON_SEL_L1_WRL2_IDLE            = 0x00000051,
+SDMA_PERFMON_SEL_L1_RDL2_IDLE            = 0x00000052,
+SDMA_PERFMON_SEL_L1_WRMC_IDLE            = 0x00000053,
+SDMA_PERFMON_SEL_L1_RDMC_IDLE            = 0x00000054,
+SDMA_PERFMON_SEL_L1_WR_INV_IDLE          = 0x00000055,
+SDMA_PERFMON_SEL_L1_RD_INV_IDLE          = 0x00000056,
+SDMA_PERFMON_SEL_META_L2_REQ_SEND        = 0x00000057,
+SDMA_PERFMON_SEL_L2_META_RET_VLD         = 0x00000058,
+SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND      = 0x00000059,
+SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN       = 0x0000005a,
+SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND      = 0x0000005b,
+SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN       = 0x0000005c,
+SDMA_PERFMON_SEL_META_REQ_SEND           = 0x0000005d,
+SDMA_PERFMON_SEL_META_RTN_VLD            = 0x0000005e,
+SDMA_PERFMON_SEL_TLBI_SEND               = 0x0000005f,
+SDMA_PERFMON_SEL_TLBI_RTN                = 0x00000060,
+SDMA_PERFMON_SEL_GCR_SEND                = 0x00000061,
+SDMA_PERFMON_SEL_GCR_RTN                 = 0x00000062,
+SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER = 0x00000063,
+SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER = 0x00000064,
+} SDMA_PERFMON_SEL;
+
+/*
+ * SDMA_PERF_SEL enum
+ */
+
+typedef enum SDMA_PERF_SEL {
+SDMA_PERF_SEL_CYCLE                      = 0x00000000,
+SDMA_PERF_SEL_IDLE                       = 0x00000001,
+SDMA_PERF_SEL_REG_IDLE                   = 0x00000002,
+SDMA_PERF_SEL_RB_EMPTY                   = 0x00000003,
+SDMA_PERF_SEL_RB_FULL                    = 0x00000004,
+SDMA_PERF_SEL_RB_WPTR_WRAP               = 0x00000005,
+SDMA_PERF_SEL_RB_RPTR_WRAP               = 0x00000006,
+SDMA_PERF_SEL_RB_WPTR_POLL_READ          = 0x00000007,
+SDMA_PERF_SEL_RB_RPTR_WB                 = 0x00000008,
+SDMA_PERF_SEL_RB_CMD_IDLE                = 0x00000009,
+SDMA_PERF_SEL_RB_CMD_FULL                = 0x0000000a,
+SDMA_PERF_SEL_IB_CMD_IDLE                = 0x0000000b,
+SDMA_PERF_SEL_IB_CMD_FULL                = 0x0000000c,
+SDMA_PERF_SEL_EX_IDLE                    = 0x0000000d,
+SDMA_PERF_SEL_SRBM_REG_SEND              = 0x0000000e,
+SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE  = 0x0000000f,
+SDMA_PERF_SEL_MC_WR_IDLE                 = 0x00000010,
+SDMA_PERF_SEL_MC_WR_COUNT                = 0x00000011,
+SDMA_PERF_SEL_MC_RD_IDLE                 = 0x00000012,
+SDMA_PERF_SEL_MC_RD_COUNT                = 0x00000013,
+SDMA_PERF_SEL_MC_RD_RET_STALL            = 0x00000014,
+SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE         = 0x00000015,
+SDMA_PERF_SEL_SEM_IDLE                   = 0x00000018,
+SDMA_PERF_SEL_SEM_REQ_STALL              = 0x00000019,
+SDMA_PERF_SEL_SEM_REQ_COUNT              = 0x0000001a,
+SDMA_PERF_SEL_SEM_RESP_INCOMPLETE        = 0x0000001b,
+SDMA_PERF_SEL_SEM_RESP_FAIL              = 0x0000001c,
+SDMA_PERF_SEL_SEM_RESP_PASS              = 0x0000001d,
+SDMA_PERF_SEL_INT_IDLE                   = 0x0000001e,
+SDMA_PERF_SEL_INT_REQ_STALL              = 0x0000001f,
+SDMA_PERF_SEL_INT_REQ_COUNT              = 0x00000020,
+SDMA_PERF_SEL_INT_RESP_ACCEPTED          = 0x00000021,
+SDMA_PERF_SEL_INT_RESP_RETRY             = 0x00000022,
+SDMA_PERF_SEL_NUM_PACKET                 = 0x00000023,
+SDMA_PERF_SEL_CE_WREQ_IDLE               = 0x00000025,
+SDMA_PERF_SEL_CE_WR_IDLE                 = 0x00000026,
+SDMA_PERF_SEL_CE_SPLIT_IDLE              = 0x00000027,
+SDMA_PERF_SEL_CE_RREQ_IDLE               = 0x00000028,
+SDMA_PERF_SEL_CE_OUT_IDLE                = 0x00000029,
+SDMA_PERF_SEL_CE_IN_IDLE                 = 0x0000002a,
+SDMA_PERF_SEL_CE_DST_IDLE                = 0x0000002b,
+SDMA_PERF_SEL_CE_AFIFO_FULL              = 0x0000002e,
+SDMA_PERF_SEL_DUMMY_0                    = 0x0000002f,
+SDMA_PERF_SEL_DUMMY_1                    = 0x00000030,
+SDMA_PERF_SEL_CE_INFO_FULL               = 0x00000031,
+SDMA_PERF_SEL_CE_INFO1_FULL              = 0x00000032,
+SDMA_PERF_SEL_CE_RD_STALL                = 0x00000033,
+SDMA_PERF_SEL_CE_WR_STALL                = 0x00000034,
+SDMA_PERF_SEL_QUEUE0_SELECT              = 0x00000035,
+SDMA_PERF_SEL_QUEUE1_SELECT              = 0x00000036,
+SDMA_PERF_SEL_QUEUE2_SELECT              = 0x00000037,
+SDMA_PERF_SEL_QUEUE3_SELECT              = 0x00000038,
+SDMA_PERF_SEL_CTX_CHANGE                 = 0x00000039,
+SDMA_PERF_SEL_CTX_CHANGE_EXPIRED         = 0x0000003a,
+SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION       = 0x0000003b,
+SDMA_PERF_SEL_DOORBELL                   = 0x0000003c,
+SDMA_PERF_SEL_RD_BA_RTR                  = 0x0000003d,
+SDMA_PERF_SEL_WR_BA_RTR                  = 0x0000003e,
+SDMA_PERF_SEL_MCU_L1_WR_VLD              = 0x0000003f,
+SDMA_PERF_SEL_CE_L1_WR_VLD               = 0x00000040,
+SDMA_PERF_SEL_CPF_SDMA_INVREQ            = 0x00000041,
+SDMA_PERF_SEL_SDMA_CPF_INVACK            = 0x00000042,
+SDMA_PERF_SEL_UTCL2_SDMA_INVREQ          = 0x00000043,
+SDMA_PERF_SEL_SDMA_UTCL2_INVACK          = 0x00000044,
+SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL      = 0x00000045,
+SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL      = 0x00000046,
+SDMA_PERF_SEL_UTCL2_RET_XNACK            = 0x00000047,
+SDMA_PERF_SEL_UTCL2_RET_ACK              = 0x00000048,
+SDMA_PERF_SEL_UTCL2_FREE                 = 0x00000049,
+SDMA_PERF_SEL_SDMA_UTCL2_SEND            = 0x0000004a,
+SDMA_PERF_SEL_DMA_L1_WR_SEND             = 0x0000004b,
+SDMA_PERF_SEL_DMA_L1_RD_SEND             = 0x0000004c,
+SDMA_PERF_SEL_DMA_MC_WR_SEND             = 0x0000004d,
+SDMA_PERF_SEL_DMA_MC_RD_SEND             = 0x0000004e,
+SDMA_PERF_SEL_GPUVM_INV_HIGH             = 0x0000004f,
+SDMA_PERF_SEL_GPUVM_INV_LOW              = 0x00000050,
+SDMA_PERF_SEL_L1_WRL2_IDLE               = 0x00000051,
+SDMA_PERF_SEL_L1_RDL2_IDLE               = 0x00000052,
+SDMA_PERF_SEL_L1_WRMC_IDLE               = 0x00000053,
+SDMA_PERF_SEL_L1_RDMC_IDLE               = 0x00000054,
+SDMA_PERF_SEL_L1_WR_INV_IDLE             = 0x00000055,
+SDMA_PERF_SEL_L1_RD_INV_IDLE             = 0x00000056,
+SDMA_PERF_SEL_META_L2_REQ_SEND           = 0x00000057,
+SDMA_PERF_SEL_L2_META_RET_VLD            = 0x00000058,
+SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND         = 0x00000059,
+SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN          = 0x0000005a,
+SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND         = 0x0000005b,
+SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN          = 0x0000005c,
+SDMA_PERF_SEL_META_REQ_SEND              = 0x0000005d,
+SDMA_PERF_SEL_META_RTN_VLD               = 0x0000005e,
+SDMA_PERF_SEL_TLBI_SEND                  = 0x0000005f,
+SDMA_PERF_SEL_TLBI_RTN                   = 0x00000060,
+SDMA_PERF_SEL_GCR_SEND                   = 0x00000061,
+SDMA_PERF_SEL_GCR_RTN                    = 0x00000062,
+SDMA_PERF_SEL_CGCG_FENCE                 = 0x00000063,
+SDMA_PERF_SEL_CE_CH_WR_REQ               = 0x00000064,
+SDMA_PERF_SEL_CE_CH_WR_RET               = 0x00000065,
+SDMA_PERF_SEL_MCU_CH_WR_REQ              = 0x00000066,
+SDMA_PERF_SEL_MCU_CH_WR_RET              = 0x00000067,
+SDMA_PERF_SEL_CE_OR_MCU_CH_RD_REQ        = 0x00000068,
+SDMA_PERF_SEL_CE_OR_MCU_CH_RD_RET        = 0x00000069,
+SDMA_PERF_SEL_RB_CH_RD_REQ               = 0x0000006a,
+SDMA_PERF_SEL_RB_CH_RD_RET               = 0x0000006b,
+SDMA_PERF_SEL_IB_CH_RD_REQ               = 0x0000006c,
+SDMA_PERF_SEL_IB_CH_RD_RET               = 0x0000006d,
+SDMA_PERF_SEL_WPTR_CH_RD_REQ             = 0x0000006e,
+SDMA_PERF_SEL_WPTR_CH_RD_RET             = 0x0000006f,
+SDMA_PERF_SEL_UTCL1_UTCL2_REQ            = 0x00000070,
+SDMA_PERF_SEL_UTCL1_UTCL2_RET            = 0x00000071,
+SDMA_PERF_SEL_CMD_OP_MATCH               = 0x00000072,
+SDMA_PERF_SEL_CMD_OP_START               = 0x00000073,
+SDMA_PERF_SEL_CMD_OP_END                 = 0x00000074,
+SDMA_PERF_SEL_CE_BUSY                    = 0x00000075,
+SDMA_PERF_SEL_CE_BUSY_START              = 0x00000076,
+SDMA_PERF_SEL_CE_BUSY_END                = 0x00000077,
+SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER        = 0x00000078,
+SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_START  = 0x00000079,
+SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_END    = 0x0000007a,
+SDMA_PERF_SEL_CE_CH_WRREQ_SEND           = 0x0000007b,
+SDMA_PERF_SEL_CH_CE_WRRET_VALID          = 0x0000007c,
+SDMA_PERF_SEL_CE_CH_RDREQ_SEND           = 0x0000007d,
+SDMA_PERF_SEL_CH_CE_RDRET_VALID          = 0x0000007e,
+SDMA_PERF_SEL_QUEUE4_SELECT              = 0x0000007f,
+SDMA_PERF_SEL_QUEUE5_SELECT              = 0x00000080,
+SDMA_PERF_SEL_QUEUE6_SELECT              = 0x00000081,
+SDMA_PERF_SEL_QUEUE7_SELECT              = 0x00000082,
+} SDMA_PERF_SEL;
+
+/*
+ * SPM_PERFMON_STATE enum
+ */
+
+typedef enum SPM_PERFMON_STATE {
+STRM_PERFMON_STATE_DISABLE_AND_RESET     = 0x00000000,
+STRM_PERFMON_STATE_START_COUNTING        = 0x00000001,
+STRM_PERFMON_STATE_STOP_COUNTING         = 0x00000002,
+STRM_PERFMON_STATE_RESERVED_3            = 0x00000003,
+STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
+STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
+} SPM_PERFMON_STATE;
+
+/*
+ * TCC_MTYPE enum
+ */
+
+typedef enum TCC_MTYPE {
+MTYPE_NC                                 = 0x00000000,
+MTYPE_WC                                 = 0x00000001,
+MTYPE_CC                                 = 0x00000002,
+} TCC_MTYPE;
+
+/*
+ * UTCL0FaultType enum
+ */
+
+typedef enum UTCL0FaultType {
+UTCL0_XNACK_SUCCESS                      = 0x00000000,
+UTCL0_XNACK_RETRY                        = 0x00000001,
+UTCL0_XNACK_PRT                          = 0x00000002,
+UTCL0_XNACK_NO_RETRY                     = 0x00000003,
+} UTCL0FaultType;
+
+/*
+ * UTCL0RequestType enum
+ */
+
+typedef enum UTCL0RequestType {
+UTCL0_TYPE_NORMAL                        = 0x00000000,
+UTCL0_TYPE_SHOOTDOWN                     = 0x00000001,
+UTCL0_TYPE_BYPASS                        = 0x00000002,
+} UTCL0RequestType;
+
+/*
+ * UTCL1FaultType enum
+ */
+
+typedef enum UTCL1FaultType {
+UTCL1_XNACK_SUCCESS                      = 0x00000000,
+UTCL1_XNACK_RETRY                        = 0x00000001,
+UTCL1_XNACK_PRT                          = 0x00000002,
+UTCL1_XNACK_NO_RETRY                     = 0x00000003,
+} UTCL1FaultType;
+
+/*
+ * UTCL1RequestType enum
+ */
+
+typedef enum UTCL1RequestType {
+UTCL1_TYPE_NORMAL                        = 0x00000000,
+UTCL1_TYPE_SHOOTDOWN                     = 0x00000001,
+UTCL1_TYPE_BYPASS                        = 0x00000002,
+} UTCL1RequestType;
+
+/*
+ * WRITE_COMPRESSION_MODE enum
+ */
+
+typedef enum WRITE_COMPRESSION_MODE {
+COMPRESSION_MODE_BYPASS_METADATA_CACHE   = 0x00000000,
+COMPRESSION_MODE_COMPRESSION_ENABLED     = 0x00000001,
+COMPRESSION_MODE_WRITE_COMPRESSION_DISABLED = 0x00000002,
+} WRITE_COMPRESSION_MODE;
+
+/*
+ * WritePolicy enum
+ */
+
+typedef enum WritePolicy {
+CACHE_LRU_WR                             = 0x00000000,
+CACHE_STREAM                             = 0x00000001,
+CACHE_NOA_WR                             = 0x00000002,
+CACHE_BYPASS                             = 0x00000003,
+} WritePolicy;
+
+/*
+ * COLOR_KEYER_ENABLE enum
+ */
+
+typedef enum COLOR_KEYER_ENABLE {
+COLOR_KEY_EN                             = 0x00000000,
+COLOR_KEY_DIS                            = 0x00000001,
+} COLOR_KEYER_ENABLE;
+
+/*
+ * COLOR_KEYER_MODE enum
+ */
+
+typedef enum COLOR_KEYER_MODE {
+FORCE_00                                 = 0x00000000,
+FORCE_FF                                 = 0x00000001,
+RANGE_00                                 = 0x00000002,
+RANGE_FF                                 = 0x00000003,
+} COLOR_KEYER_MODE;
+
+/*
+ * DENORM_TRUNCATE enum
+ */
+
+typedef enum DENORM_TRUNCATE {
+CNVC_ROUND                               = 0x00000000,
+CNVC_TRUNCATE                            = 0x00000001,
+} DENORM_TRUNCATE;
+
+/*
+ * FORMAT_CROSSBAR enum
+ */
+
+typedef enum FORMAT_CROSSBAR {
+FORMAT_CROSSBAR_R                        = 0x00000000,
+FORMAT_CROSSBAR_G                        = 0x00000001,
+FORMAT_CROSSBAR_B                        = 0x00000002,
+} FORMAT_CROSSBAR;
+
+/*
+ * LUMA_KEYER_ENABLE enum
+ */
+
+typedef enum LUMA_KEYER_ENABLE {
+LUMA_KEY_EN                              = 0x00000000,
+LUMA_KEY_DIS                             = 0x00000001,
+} LUMA_KEYER_ENABLE;
+
+/*
+ * PIX_EXPAND_MODE enum
+ */
+
+typedef enum PIX_EXPAND_MODE {
+PIX_DYNAMIC_EXPANSION                    = 0x00000000,
+PIX_ZERO_EXPANSION                       = 0x00000001,
+} PIX_EXPAND_MODE;
+
+/*
+ * PRE_CSC_MODE_ENUM enum
+ */
+
+typedef enum PRE_CSC_MODE_ENUM {
+PRE_CSC_BYPASS                           = 0x00000000,
+PRE_CSC_SET_A                            = 0x00000001,
+PRE_CSC_SET_B                            = 0x00000002,
+} PRE_CSC_MODE_ENUM;
+
+/*
+ * PRE_DEGAM_MODE enum
+ */
+
+typedef enum PRE_DEGAM_MODE {
+PRE_DEGAM_BYPASS                         = 0x00000000,
+PRE_DEGAM_ENABLE                         = 0x00000001,
+} PRE_DEGAM_MODE;
+
+/*
+ * PRE_DEGAM_SELECT enum
+ */
+
+typedef enum PRE_DEGAM_SELECT {
+PRE_DEGAM_SRGB                           = 0x00000000,
+PRE_DEGAM_GAMMA_22                       = 0x00000001,
+PRE_DEGAM_GAMMA_24                       = 0x00000002,
+PRE_DEGAM_GAMMA_26                       = 0x00000003,
+PRE_DEGAM_BT2020                         = 0x00000004,
+PRE_DEGAM_BT2100PQ                       = 0x00000005,
+PRE_DEGAM_BT2100HLG                      = 0x00000006,
+} PRE_DEGAM_SELECT;
+
+/*
+ * SURFACE_PIXEL_FORMAT enum
+ */
+
+typedef enum SURFACE_PIXEL_FORMAT {
+ARGB1555                                 = 0x00000001,
+RGBA5551                                 = 0x00000002,
+RGB565                                   = 0x00000003,
+BGR565                                   = 0x00000004,
+ARGB4444                                 = 0x00000005,
+RGBA4444                                 = 0x00000006,
+ARGB8888                                 = 0x00000008,
+RGBA8888                                 = 0x00000009,
+ARGB2101010                              = 0x0000000a,
+RGBA1010102                              = 0x0000000b,
+AYCrCb8888                               = 0x0000000c,
+YCrCbA8888                               = 0x0000000d,
+ACrYCb8888                               = 0x0000000e,
+CrYCbA8888                               = 0x0000000f,
+ARGB16161616_10MSB                       = 0x00000010,
+RGBA16161616_10MSB                       = 0x00000011,
+ARGB16161616_10LSB                       = 0x00000012,
+RGBA16161616_10LSB                       = 0x00000013,
+ARGB16161616_12MSB                       = 0x00000014,
+RGBA16161616_12MSB                       = 0x00000015,
+ARGB16161616_12LSB                       = 0x00000016,
+RGBA16161616_12LSB                       = 0x00000017,
+ARGB16161616_FLOAT                       = 0x00000018,
+RGBA16161616_FLOAT                       = 0x00000019,
+ARGB16161616_UNORM                       = 0x0000001a,
+RGBA16161616_UNORM                       = 0x0000001b,
+ARGB16161616_SNORM                       = 0x0000001c,
+RGBA16161616_SNORM                       = 0x0000001d,
+AYCrCb16161616_10MSB                     = 0x00000020,
+AYCrCb16161616_10LSB                     = 0x00000021,
+YCrCbA16161616_10MSB                     = 0x00000022,
+YCrCbA16161616_10LSB                     = 0x00000023,
+ACrYCb16161616_10MSB                     = 0x00000024,
+ACrYCb16161616_10LSB                     = 0x00000025,
+CrYCbA16161616_10MSB                     = 0x00000026,
+CrYCbA16161616_10LSB                     = 0x00000027,
+AYCrCb16161616_12MSB                     = 0x00000028,
+AYCrCb16161616_12LSB                     = 0x00000029,
+YCrCbA16161616_12MSB                     = 0x0000002a,
+YCrCbA16161616_12LSB                     = 0x0000002b,
+ACrYCb16161616_12MSB                     = 0x0000002c,
+ACrYCb16161616_12LSB                     = 0x0000002d,
+CrYCbA16161616_12MSB                     = 0x0000002e,
+CrYCbA16161616_12LSB                     = 0x0000002f,
+Y8_CrCb88_420_PLANAR                     = 0x00000040,
+Y8_CbCr88_420_PLANAR                     = 0x00000041,
+Y10_CrCb1010_420_PLANAR                  = 0x00000042,
+Y10_CbCr1010_420_PLANAR                  = 0x00000043,
+Y12_CrCb1212_420_PLANAR                  = 0x00000044,
+Y12_CbCr1212_420_PLANAR                  = 0x00000045,
+YCrYCb8888_422_PACKED                    = 0x00000048,
+YCbYCr8888_422_PACKED                    = 0x00000049,
+CrYCbY8888_422_PACKED                    = 0x0000004a,
+CbYCrY8888_422_PACKED                    = 0x0000004b,
+YCrYCb10101010_422_PACKED                = 0x0000004c,
+YCbYCr10101010_422_PACKED                = 0x0000004d,
+CrYCbY10101010_422_PACKED                = 0x0000004e,
+CbYCrY10101010_422_PACKED                = 0x0000004f,
+YCrYCb12121212_422_PACKED                = 0x00000050,
+YCbYCr12121212_422_PACKED                = 0x00000051,
+CrYCbY12121212_422_PACKED                = 0x00000052,
+CbYCrY12121212_422_PACKED                = 0x00000053,
+RGB111110_FIX                            = 0x00000070,
+BGR101111_FIX                            = 0x00000071,
+ACrYCb2101010                            = 0x00000072,
+CrYCbA1010102                            = 0x00000073,
+RGBE                                     = 0x00000074,
+RGB111110_FLOAT                          = 0x00000076,
+BGR101111_FLOAT                          = 0x00000077,
+MONO_8                                   = 0x00000078,
+MONO_10MSB                               = 0x00000079,
+MONO_10LSB                               = 0x0000007a,
+MONO_12MSB                               = 0x0000007b,
+MONO_12LSB                               = 0x0000007c,
+MONO_16                                  = 0x0000007d,
+} SURFACE_PIXEL_FORMAT;
+
+/*
+ * XNORM enum
+ */
+
+typedef enum XNORM {
+XNORM_A                                  = 0x00000000,
+XNORM_B                                  = 0x00000001,
+} XNORM;
+
+/*
+ * CUR_ENABLE enum
+ */
+
+typedef enum CUR_ENABLE {
+CUR_DIS                                  = 0x00000000,
+CUR_EN                                   = 0x00000001,
+} CUR_ENABLE;
+
+/*
+ * CUR_EXPAND_MODE enum
+ */
+
+typedef enum CUR_EXPAND_MODE {
+CUR_DYNAMIC_EXPANSION                    = 0x00000000,
+CUR_ZERO_EXPANSION                       = 0x00000001,
+} CUR_EXPAND_MODE;
+
+/*
+ * CUR_INV_CLAMP enum
+ */
+
+typedef enum CUR_INV_CLAMP {
+CUR_CLAMP_DIS                            = 0x00000000,
+CUR_CLAMP_EN                             = 0x00000001,
+} CUR_INV_CLAMP;
+
+/*
+ * CUR_MATRIX_COEF_FORMAT_ENUM enum
+ */
+
+typedef enum CUR_MATRIX_COEF_FORMAT_ENUM {
+CUR_MATRIX_FIX_S2_13                     = 0x00000000,
+CUR_MATRIX_FIX_S3_12                     = 0x00000001,
+} CUR_MATRIX_COEF_FOR