diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2024-04-14 22:34:03 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-05-08 15:17:07 -0400 |
| commit | 1dd8b24acc0f951d9fea1b03d0c9ac4630a82e44 (patch) | |
| tree | 68b7d286c46d49c1e414adc0a0ba6d99681a750c /drivers/gpu/drm/amd | |
| parent | c866201cdc2a05a7fe94009eda2644ceb54e8303 (diff) | |
| download | linux-1dd8b24acc0f951d9fea1b03d0c9ac4630a82e44.tar.gz linux-1dd8b24acc0f951d9fea1b03d0c9ac4630a82e44.tar.bz2 linux-1dd8b24acc0f951d9fea1b03d0c9ac4630a82e44.zip | |
drm/amdgpu/nv: use common nbio callback to set remap offset
This fixes HDP flushes on systems with non-4K pages.
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nv.c | 6 |
3 files changed, 1 insertions, 13 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c index 41ae0a6f9db8..fa479dfa1ec1 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c @@ -339,10 +339,6 @@ static void nbio_v2_3_init_registers(struct amdgpu_device *adev) if (def != data) WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); - - if (amdgpu_sriov_vf(adev)) - adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, - mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; } #define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT 0x00000000 // off by default, no gains over L1 diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c index 52774a096350..a766e2d90cd0 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c @@ -402,10 +402,6 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev) WREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2, data); break; } - - if (amdgpu_sriov_vf(adev)) - adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, - regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; } #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 12e54047bf79..7e30a89fe03e 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -637,13 +637,9 @@ static const struct amdgpu_asic_funcs nv_asic_funcs = { static int nv_common_early_init(void *handle) { -#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) struct amdgpu_device *adev = (struct amdgpu_device *)handle; - if (!amdgpu_sriov_vf(adev)) { - adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; - adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; - } + adev->nbio.funcs->set_reg_remap(adev); adev->smc_rreg = NULL; adev->smc_wreg = NULL; adev->pcie_rreg = &amdgpu_device_indirect_rreg; |