diff options
| author | Anusha Srivatsa <anusha.srivatsa@intel.com> | 2021-05-18 14:34:41 -0700 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2021-05-19 18:46:58 -0700 |
| commit | ec2b1485a06519308921ce0e67d802bbc920c711 (patch) | |
| tree | b2626722924e878a469ca298765eecf4112558f3 /drivers/gpu/drm/i915/display/intel_csr.c | |
| parent | c24760cf42c3ccfc242dc1c7d82cf5a55c3cb0ff (diff) | |
| download | linux-ec2b1485a06519308921ce0e67d802bbc920c711.tar.gz linux-ec2b1485a06519308921ce0e67d802bbc920c711.tar.bz2 linux-ec2b1485a06519308921ce0e67d802bbc920c711.zip | |
drm/i915/dmc: s/HAS_CSR/HAS_DMC
No functional change.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210518213444.11420-3-anusha.srivatsa@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_csr.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_csr.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c index a22339ebdffd..5ed286dc6720 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.c +++ b/drivers/gpu/drm/i915/display/intel_csr.c @@ -315,9 +315,9 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv) u32 *payload = dev_priv->dmc.dmc_payload; u32 i, fw_size; - if (!HAS_CSR(dev_priv)) { + if (!HAS_DMC(dev_priv)) { drm_err(&dev_priv->drm, - "No CSR support available for this platform\n"); + "No DMC support available for this platform\n"); return; } @@ -686,7 +686,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) INIT_WORK(&dev_priv->dmc.work, csr_load_work_fn); - if (!HAS_CSR(dev_priv)) + if (!HAS_DMC(dev_priv)) return; /* @@ -776,7 +776,7 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) */ void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv) { - if (!HAS_CSR(dev_priv)) + if (!HAS_DMC(dev_priv)) return; flush_work(&dev_priv->dmc.work); @@ -795,7 +795,7 @@ void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv) */ void intel_csr_ucode_resume(struct drm_i915_private *dev_priv) { - if (!HAS_CSR(dev_priv)) + if (!HAS_DMC(dev_priv)) return; /* @@ -815,7 +815,7 @@ void intel_csr_ucode_resume(struct drm_i915_private *dev_priv) */ void intel_csr_ucode_fini(struct drm_i915_private *dev_priv) { - if (!HAS_CSR(dev_priv)) + if (!HAS_DMC(dev_priv)) return; intel_csr_ucode_suspend(dev_priv); |