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| author | Imre Deak <imre.deak@intel.com> | 2024-06-26 20:08:13 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2024-06-28 12:50:52 +0300 |
| commit | 32a120f52a4c0121bca8f2328d4680d283693d60 (patch) | |
| tree | 22188711592eb6ff7d8549bc97539761d5070934 /drivers/gpu/drm/i915/display/intel_ddi.c | |
| parent | a9422ec92a6388c8a19fad759f7ed0d533734cc6 (diff) | |
| download | linux-32a120f52a4c0121bca8f2328d4680d283693d60.tar.gz linux-32a120f52a4c0121bca8f2328d4680d283693d60.tar.bz2 linux-32a120f52a4c0121bca8f2328d4680d283693d60.zip | |
drm/i915/mtl: Skip PLL state verification in TBT mode
In TBT-alt mode the driver doesn't program the PHY's PLL, which is
handled instead by Thunderbolt driver/FW components, hence the PLL's HW
vs. SW state verification should be skipped. During HW readout set a flag
in the PLL state if the port was at the moment in TBT-alt mode and skip
the verification of PLL parameters in this case.
Fixes: 45fe957ae769 ("drm/i915/display: Add compare config for MTL+ platforms")
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11258
Cc: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240626170813.806470-1-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_ddi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_ddi.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 6672fc162c4f..a07aca96e551 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4027,14 +4027,12 @@ void intel_ddi_get_clock(struct intel_encoder *encoder, static void mtl_ddi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { - struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); - if (intel_tc_port_in_tbt_alt_mode(dig_port)) { + if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); - } else { - intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); + else crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); - } intel_ddi_get_config(encoder, crtc_state); } |