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authorJouni Högander <jouni.hogander@intel.com>2024-05-17 10:30:03 +0300
committerJouni Högander <jouni.hogander@intel.com>2024-05-20 07:34:45 +0300
commit45430e7b7c8de9ed910d99cc8906db3db5a1334d (patch)
treef9a91a061ede07280014121f3ecd7b7949d47b6c /drivers/gpu/drm/i915/display/intel_psr.c
parent007ed70831426d4cc108d879d688de6b8e3e6d45 (diff)
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drm/i915/psr: LunarLake IO and Fast Wake time line count maximums are 68
On LunarLake maximum for IO and Fast Wake time line counts are 68: 6 bits + 5 lines added by the HW. Take this into account in calculation and when writing the IO Wake lines. v2: maximum line count is 68 (6 bits + 5 lines added by HW) Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-2-jouni.hogander@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_psr.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_psr.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index df0d14a5023f..f5d3eb776833 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1421,8 +1421,9 @@ static bool _compute_alpm_params(struct intel_dp *intel_dp,
fast_wake_time = precharge + preamble + phy_wake +
tfw_exit_latency;
- if (DISPLAY_VER(i915) >= 12)
- /* TODO: Check how we can use ALPM_CTL fast wake extended field */
+ if (DISPLAY_VER(i915) >= 20)
+ max_wake_lines = 68;
+ else if (DISPLAY_VER(i915) >= 12)
max_wake_lines = 12;
else
max_wake_lines = 8;