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| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2024-03-19 23:03:02 -0700 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2024-03-22 14:14:56 -0700 |
| commit | 326e30e4624c1f15855d8241bc639c0a0cea7429 (patch) | |
| tree | 6cadb194f8149b7e5918bf5aa118a9bf1f7ece6f /drivers/gpu/drm/i915/gt/intel_workarounds.c.rej | |
| parent | 48ba4a6dc3876f87090ccfe942c6d8325f49e11c (diff) | |
| download | linux-326e30e4624c1f15855d8241bc639c0a0cea7429.tar.gz linux-326e30e4624c1f15855d8241bc639c0a0cea7429.tar.bz2 linux-326e30e4624c1f15855d8241bc639c0a0cea7429.zip | |
drm/i915: Drop dead code for pvc
PCI IDs for PVC were never added and platform always marked with
force_probe. Drop what's not used and rename some places as needed.
The registers not used anymore are also removed.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Tvrtko Ursulin <tursulin@ursulin.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20240320060543.4034215-6-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_workarounds.c.rej')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_workarounds.c.rej | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c.rej b/drivers/gpu/drm/i915/gt/intel_workarounds.c.rej new file mode 100644 index 000000000000..91463b1d684a --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c.rej @@ -0,0 +1,18 @@ +diff a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c (rejected hunks) +@@ -2844,14 +2767,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li + + if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || + IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) || +- IS_PONTEVECCHIO(i915) || + IS_DG2(i915)) { + /* Wa_22014226127 */ + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); + } + +- if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) +- /* Wa_14015227452:dg2,pvc */ ++ if (IS_DG2(i915)) ++ /* Wa_14015227452 */ + wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); + + if (IS_DG2(i915)) { |