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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2021-03-31 13:57:34 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2021-04-07 11:05:46 -0700 |
| commit | 6e2ad9c3bfca3e43f0b66c85385f12bd254ef92d (patch) | |
| tree | a0646645503e3c9e7884c98b36f3a684471311fc /drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | |
| parent | 001d8dc33875593e85e54206f7dd91ecca1204a7 (diff) | |
| download | linux-6e2ad9c3bfca3e43f0b66c85385f12bd254ef92d.tar.gz linux-6e2ad9c3bfca3e43f0b66c85385f12bd254ef92d.tar.bz2 linux-6e2ad9c3bfca3e43f0b66c85385f12bd254ef92d.zip | |
drm/msm/dsi: inline msm_dsi_phy_set_src_pll
The src_truthtable config is not used for some of phys, which use other
means of configuring the master/slave usecases. Inline this function
with the goal of removing src_pll_id argument in the next commit.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Link: https://lore.kernel.org/r/20210331105735.3690009-24-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/dsi/phy/dsi_phy.h')
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 7748f8b5ea53..00ef01baaebd 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -33,12 +33,6 @@ struct msm_dsi_phy_cfg { unsigned long min_pll_rate; unsigned long max_pll_rate; - /* - * Each cell {phy_id, pll_id} of the truth table indicates - * if the source PLL selection bit should be set for each PHY. - * Fill default H/W values in illegal cells, eg. cell {0, 1}. - */ - bool src_pll_truthtable[DSI_MAX][DSI_MAX]; const resource_size_t io_start[DSI_MAX]; const int num_dsi_phy; const int quirks; @@ -121,7 +115,5 @@ int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, struct msm_dsi_phy_clk_request *clk_req); int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, struct msm_dsi_phy_clk_request *clk_req); -void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg, - u32 bit_mask); #endif /* __DSI_PHY_H__ */ |