drm/msm/dsi: drop msm_dsi_pll abstraction

Drop the struct msm_dsi_pll abstraction, by including vco's clk_hw
directly into struct msm_dsi_phy.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210331105735.3690009-19-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>

1 files changed, 35 insertions, 31 deletions

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index fefff08f83fd..cbf3d64d5efb 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -7,7 +7,6 @@
 #include <linux/clk-provider.h>
 #include <linux/iopoll.h>
 
-#include "dsi_pll.h"
 #include "dsi_phy.h"
 #include "dsi.xml.h"
 
@@ -85,11 +84,13 @@ struct pll_10nm_cached_state {
 };
 
 struct dsi_pll_10nm {
-	struct msm_dsi_pll base;
+	struct clk_hw clk_hw;
 
 	int id;
 	struct platform_device *pdev;
 
+	struct msm_dsi_phy *phy;
+
 	void __iomem *phy_cmn_mmio;
 	void __iomem *mmio;
 
@@ -104,11 +105,10 @@ struct dsi_pll_10nm {
 
 	struct pll_10nm_cached_state cached_state;
 
-	enum msm_dsi_phy_usecase uc;
 	struct dsi_pll_10nm *slave;
 };
 
-#define to_pll_10nm(x)	container_of(x, struct dsi_pll_10nm, base)
+#define to_pll_10nm(x)	container_of(x, struct dsi_pll_10nm, clk_hw)
 
 /*
  * Global list of private DSI PLL struct pointers. We need this for Dual DSI
@@ -302,8 +302,7 @@ static void dsi_pll_commit(struct dsi_pll_10nm *pll)
 static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
 				     unsigned long parent_rate)
 {
-	struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
-	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
+	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
 
 	DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->id, rate,
 	    parent_rate);
@@ -390,8 +389,7 @@ static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll)
 
 static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
 {
-	struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
-	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
+	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
 	struct device *dev = &pll_10nm->pdev->dev;
 	int rc;
 
@@ -422,7 +420,7 @@ static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
 		goto error;
 	}
 
-	pll->pll_on = true;
+	pll_10nm->phy->pll_on = true;
 
 	dsi_pll_enable_global_clk(pll_10nm);
 	if (pll_10nm->slave)
@@ -446,8 +444,7 @@ static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll)
 
 static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw)
 {
-	struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
-	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
+	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
 
 	/*
 	 * To avoid any stray glitches while abruptly powering down the PLL
@@ -463,14 +460,13 @@ static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw)
 	}
 	/* flush, ensure all register writes are done */
 	wmb();
-	pll->pll_on = false;
+	pll_10nm->phy->pll_on = false;
 }
 
 static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
 						  unsigned long parent_rate)
 {
-	struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
-	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
+	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
 	struct dsi_pll_config *config = &pll_10nm->pll_configuration;
 	void __iomem *base = pll_10nm->mmio;
 	u64 ref_clk = pll_10nm->vco_ref_clk_rate;
@@ -506,8 +502,21 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
 	return (unsigned long)vco_rate;
 }
 
+static long dsi_pll_10nm_clk_round_rate(struct clk_hw *hw,
+		unsigned long rate, unsigned long *parent_rate)
+{
+	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
+
+	if      (rate < pll_10nm->phy->cfg->min_pll_rate)
+		return  pll_10nm->phy->cfg->min_pll_rate;
+	else if (rate > pll_10nm->phy->cfg->max_pll_rate)
+		return  pll_10nm->phy->cfg->max_pll_rate;
+	else
+		return rate;
+}
+
 static const struct clk_ops clk_ops_dsi_pll_10nm_vco = {
-	.round_rate = msm_dsi_pll_helper_clk_round_rate,
+	.round_rate = dsi_pll_10nm_clk_round_rate,
 	.set_rate = dsi_pll_10nm_vco_set_rate,
 	.recalc_rate = dsi_pll_10nm_vco_recalc_rate,
 	.prepare = dsi_pll_10nm_vco_prepare,
@@ -520,7 +529,7 @@ static const struct clk_ops clk_ops_dsi_pll_10nm_vco = {
 
 static void dsi_10nm_pll_save_state(struct msm_dsi_phy *phy)
 {
-	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll);
+	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
 	struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
 	void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
 	u32 cmn_clk_cfg0, cmn_clk_cfg1;
@@ -543,7 +552,7 @@ static void dsi_10nm_pll_save_state(struct msm_dsi_phy *phy)
 
 static int dsi_10nm_pll_restore_state(struct msm_dsi_phy *phy)
 {
-	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->pll);
+	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
 	struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
 	void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
 	u32 val;
@@ -562,7 +571,7 @@ static int dsi_10nm_pll_restore_state(struct msm_dsi_phy *phy)
 	val |= cached->pll_mux;
 	pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);
 
-	ret = dsi_pll_10nm_vco_set_rate(&phy->pll->clk_hw,
+	ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw,
 			pll_10nm->vco_current_rate,
 			pll_10nm->vco_ref_clk_rate);
 	if (ret) {
@@ -576,16 +585,15 @@ static int dsi_10nm_pll_restore_state(struct msm_dsi_phy *phy)
 	return 0;
 }
 
-static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll,
-				    enum msm_dsi_phy_usecase uc)
+static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy)
 {
-	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
+	struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
 	void __iomem *base = pll_10nm->phy_cmn_mmio;
 	u32 data = 0x0;	/* internal PLL */
 
 	DBG("DSI PLL%d", pll_10nm->id);
 
-	switch (uc) {
+	switch (phy->usecase) {
 	case MSM_DSI_PHY_STANDALONE:
 		break;
 	case MSM_DSI_PHY_MASTER:
@@ -601,8 +609,6 @@ static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll,
 	/* set PLL src */
 	pll_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2));
 
-	pll_10nm->uc = uc;
-
 	return 0;
 }
 
@@ -630,9 +636,9 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
 	DBG("DSI%d", pll_10nm->id);
 
 	snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id);
-	pll_10nm->base.clk_hw.init = &vco_init;
+	pll_10nm->clk_hw.init = &vco_init;
 
-	ret = devm_clk_hw_register(dev, &pll_10nm->base.clk_hw);
+	ret = devm_clk_hw_register(dev, &pll_10nm->clk_hw);
 	if (ret)
 		return ret;
 
@@ -742,7 +748,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
 	struct platform_device *pdev = phy->pdev;
 	int id = phy->id;
 	struct dsi_pll_10nm *pll_10nm;
-	struct msm_dsi_pll *pll;
 	int ret;
 
 	pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL);
@@ -769,8 +774,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
 
 	spin_lock_init(&pll_10nm->postdiv_lock);
 
-	pll = &pll_10nm->base;
-	pll->cfg = phy->cfg;
+	pll_10nm->phy = phy;
 
 	ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws);
 	if (ret) {
@@ -778,7 +782,7 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
 		return ret;
 	}
 
-	phy->pll = pll;
+	phy->vco_hw = &pll_10nm->clk_hw;
 
 	/* TODO: Remove this when we have proper display handover support */
 	msm_dsi_phy_pll_save_state(phy);
@@ -953,7 +957,7 @@ static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
 	/* Select full-rate mode */
 	dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_2, 0x40);
 
-	ret = dsi_pll_10nm_set_usecase(phy->pll, phy->usecase);
+	ret = dsi_10nm_set_usecase(phy);
 	if (ret) {
 		DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
 			__func__, ret);