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authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>2021-03-31 13:57:19 +0300
committerRob Clark <robdclark@chromium.org>2021-04-07 11:05:45 -0700
commit076437c9e360737c85d443bbf81d5ea02b3d182d (patch)
tree20a0c62b459a63d149a41fb5b98b243fbfd24cfb /drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
parent80d2229bf0e7b169a1ab3adcaed9c4ce336f50b2 (diff)
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drm/msm/dsi: move min/max PLL rate to phy config
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor Link: https://lore.kernel.org/r/20210331105735.3690009-9-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c')
-rw-r--r--drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index dc8ccc994759..5f9d0cfc4e03 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -864,8 +864,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
spin_lock_init(&pll_10nm->postdiv_lock);
pll = &pll_10nm->base;
- pll->min_rate = 1000000000UL;
- pll->max_rate = 3500000000UL;
pll->cfg = phy->cfg;
pll_10nm->vco_delay = 1;
@@ -1113,6 +1111,8 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
.restore_state = dsi_pll_10nm_restore_state,
.set_usecase = dsi_pll_10nm_set_usecase,
},
+ .min_pll_rate = 1000000000UL,
+ .max_pll_rate = 3500000000UL,
.io_start = { 0xae94400, 0xae96400 },
.num_dsi_phy = 2,
};
@@ -1138,6 +1138,8 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
.restore_state = dsi_pll_10nm_restore_state,
.set_usecase = dsi_pll_10nm_set_usecase,
},
+ .min_pll_rate = 1000000000UL,
+ .max_pll_rate = 3500000000UL,
.io_start = { 0xc994400, 0xc996400 },
.num_dsi_phy = 2,
.quirks = DSI_PHY_10NM_QUIRK_OLD_TIMINGS,