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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2021-03-31 13:57:34 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2021-04-07 11:05:46 -0700 |
| commit | 6e2ad9c3bfca3e43f0b66c85385f12bd254ef92d (patch) | |
| tree | a0646645503e3c9e7884c98b36f3a684471311fc /drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | |
| parent | 001d8dc33875593e85e54206f7dd91ecca1204a7 (diff) | |
| download | linux-6e2ad9c3bfca3e43f0b66c85385f12bd254ef92d.tar.gz linux-6e2ad9c3bfca3e43f0b66c85385f12bd254ef92d.tar.bz2 linux-6e2ad9c3bfca3e43f0b66c85385f12bd254ef92d.zip | |
drm/msm/dsi: inline msm_dsi_phy_set_src_pll
The src_truthtable config is not used for some of phys, which use other
means of configuring the master/slave usecases. Inline this function
with the goal of removing src_pll_id argument in the next commit.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Link: https://lore.kernel.org/r/20210331105735.3690009-24-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c')
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c index 5e73f811d645..f5b88c85a8fc 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c @@ -70,6 +70,7 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, int i; void __iomem *base = phy->base; u32 cfg_4[4] = {0x20, 0x40, 0x20, 0x00}; + u32 val; DBG(""); @@ -83,9 +84,12 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff); - msm_dsi_phy_set_src_pll(phy, src_pll_id, - REG_DSI_20nm_PHY_GLBL_TEST_CTRL, - DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL); + val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL); + if (src_pll_id == DSI_1) + val |= DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL; + else + val &= ~DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL; + dsi_phy_write(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL, val); for (i = 0; i < 4; i++) { dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i), @@ -125,7 +129,6 @@ static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy) } const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = { - .src_pll_truthtable = { {false, true}, {false, true} }, .has_phy_regulator = true, .reg_cfg = { .num = 2, |