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author | Jyri Sarha <jsarha@ti.com> | 2016-06-07 15:09:15 +0300 |
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committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2016-06-07 17:10:49 +0300 |
commit | acc3a231d3d145b23d1f975b9be89b7cfb09885b (patch) | |
tree | 0c8ff7ff364413e528a1ffb4cdf08263aacd7576 /drivers/gpu/drm/omapdrm/dss/omapdss.h | |
parent | f8ed34ac7b453296cf36d6eb7ae911de353e1351 (diff) | |
download | linux-acc3a231d3d145b23d1f975b9be89b7cfb09885b.tar.gz linux-acc3a231d3d145b23d1f975b9be89b7cfb09885b.tar.bz2 linux-acc3a231d3d145b23d1f975b9be89b7cfb09885b.zip |
drm/omapdrm: Add gamma table support to DSS dispc
Add gamma table support to DSS dispc.
DSS driver initializes the default gamma table at component bind time
and holds a copy of all gamma tables in its internal data structure.
Each call to dispc_mgr_set_gamma() updates the internal table and
triggers write to the HW, if it is enabled. The tables are restored to
HW in PM resume callback. The drivers internal data structure match
the HW tables in size and in number of significant bits per color
component. The dispc_mgr_set_gamma() converts the size of any given
table for the internal data structure using linear interpolation.
Default gamma table is restored if NULL is given in place of gamma
lut.
dispc_mgr_gamma_size() gives HW gamma table size for the channel and
returns 0 if gamma table is not supported by the HW or the DSS driver.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/gpu/drm/omapdrm/dss/omapdss.h')
-rw-r--r-- | drivers/gpu/drm/omapdrm/dss/omapdss.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index 9263283952b9..6eaf1adbd606 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -24,6 +24,7 @@ #include <linux/interrupt.h> #include <video/videomode.h> #include <linux/platform_data/omapdss.h> +#include <uapi/drm/drm_mode.h> #define DISPC_IRQ_FRAMEDONE (1 << 0) #define DISPC_IRQ_VSYNC (1 << 1) @@ -908,6 +909,10 @@ void dispc_mgr_set_timings(enum omap_channel channel, const struct omap_video_timings *timings); void dispc_mgr_setup(enum omap_channel channel, const struct omap_overlay_manager_info *info); +u32 dispc_mgr_gamma_size(enum omap_channel channel); +void dispc_mgr_set_gamma(enum omap_channel channel, + const struct drm_color_lut *lut, + unsigned int length); int dispc_ovl_enable(enum omap_plane plane, bool enable); bool dispc_ovl_enabled(enum omap_plane plane); |