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| author | Ingo Molnar <mingo@kernel.org> | 2017-08-29 11:42:07 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2017-08-29 11:42:07 +0200 |
| commit | 416b0c0faf634abc09568885cb95266ce669c606 (patch) | |
| tree | bf63b94f57246fbf264c93bfdd6233395b07ef89 /drivers/iio/adc/stm32-adc-core.c | |
| parent | c0bb80cfa3c37fd92f066e328d83656067519a5f (diff) | |
| parent | 9c3a815f471a84811cf8021cf64aae3b8081dfde (diff) | |
| download | linux-416b0c0faf634abc09568885cb95266ce669c606.tar.gz linux-416b0c0faf634abc09568885cb95266ce669c606.tar.bz2 linux-416b0c0faf634abc09568885cb95266ce669c606.zip | |
Merge branch 'linus' into x86/apic, to pick up fixes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'drivers/iio/adc/stm32-adc-core.c')
| -rw-r--r-- | drivers/iio/adc/stm32-adc-core.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c index e09233b03c05..609676384f5e 100644 --- a/drivers/iio/adc/stm32-adc-core.c +++ b/drivers/iio/adc/stm32-adc-core.c @@ -64,7 +64,7 @@ #define STM32H7_CKMODE_MASK GENMASK(17, 16) /* STM32 H7 maximum analog clock rate (from datasheet) */ -#define STM32H7_ADC_MAX_CLK_RATE 72000000 +#define STM32H7_ADC_MAX_CLK_RATE 36000000 /** * stm32_adc_common_regs - stm32 common registers, compatible dependent data @@ -148,14 +148,14 @@ static int stm32f4_adc_clk_sel(struct platform_device *pdev, return -EINVAL; } - priv->common.rate = rate; + priv->common.rate = rate / stm32f4_pclk_div[i]; val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR); val &= ~STM32F4_ADC_ADCPRE_MASK; val |= i << STM32F4_ADC_ADCPRE_SHIFT; writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR); dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n", - rate / (stm32f4_pclk_div[i] * 1000)); + priv->common.rate / 1000); return 0; } @@ -250,7 +250,7 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev, out: /* rate used later by each ADC instance to control BOOST mode */ - priv->common.rate = rate; + priv->common.rate = rate / div; /* Set common clock mode and prescaler */ val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR); @@ -260,7 +260,7 @@ out: writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR); dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n", - ckmode ? "bus" : "adc", div, rate / (div * 1000)); + ckmode ? "bus" : "adc", div, priv->common.rate / 1000); return 0; } |