cxl: Remove driver

Remove the cxl driver that provides support for the IBM Coherent
Accelerator Processor Interface. Revert or clean up associated code in
arch/powerpc that is no longer necessary.

cxl has received minimal maintenance for several years, and is not
supported on the Power10 processor. We aren't aware of any users who are
likely to be using recent kernels.

Thanks to Mikey Neuling, Ian Munsie, Daniel Axtens, Frederic Barrat,
Christophe Lombard, Philippe Bergheaud, Vaibhav Jain and Alastair
D'Silva for their work on this driver over the years.

Signed-off-by: Andrew Donnellan <ajd@linux.ibm.com>
Acked-by: Frederic Barrat <fbarrat@linux.ibm.com>
Acked-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://patch.msgid.link/20250219070007.177725-2-ajd@linux.ibm.com

1 files changed, 0 insertions, 2103 deletions

diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
deleted file mode 100644
index 92bf7c5c7b35..000000000000
--- a/drivers/misc/cxl/pci.c
+++ /dev/null
@@ -1,2103 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2014 IBM Corp.
- */
-
-#include <linux/pci_regs.h>
-#include <linux/pci_ids.h>
-#include <linux/device.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/sort.h>
-#include <linux/pci.h>
-#include <linux/of.h>
-#include <linux/delay.h>
-#include <asm/opal.h>
-#include <asm/msi_bitmap.h>
-#include <asm/pnv-pci.h>
-#include <asm/io.h>
-#include <asm/reg.h>
-
-#include "cxl.h"
-#include <misc/cxl.h>
-
-
-#define CXL_PCI_VSEC_ID	0x1280
-#define CXL_VSEC_MIN_SIZE 0x80
-
-#define CXL_READ_VSEC_LENGTH(dev, vsec, dest)			\
-	{							\
-		pci_read_config_word(dev, vsec + 0x6, dest);	\
-		*dest >>= 4;					\
-	}
-#define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
-	pci_read_config_byte(dev, vsec + 0x8, dest)
-
-#define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
-	pci_read_config_byte(dev, vsec + 0x9, dest)
-#define CXL_STATUS_SECOND_PORT  0x80
-#define CXL_STATUS_MSI_X_FULL   0x40
-#define CXL_STATUS_MSI_X_SINGLE 0x20
-#define CXL_STATUS_FLASH_RW     0x08
-#define CXL_STATUS_FLASH_RO     0x04
-#define CXL_STATUS_LOADABLE_AFU 0x02
-#define CXL_STATUS_LOADABLE_PSL 0x01
-/* If we see these features we won't try to use the card */
-#define CXL_UNSUPPORTED_FEATURES \
-	(CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
-
-#define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
-	pci_read_config_byte(dev, vsec + 0xa, dest)
-#define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
-	pci_write_config_byte(dev, vsec + 0xa, val)
-#define CXL_VSEC_PROTOCOL_MASK   0xe0
-#define CXL_VSEC_PROTOCOL_1024TB 0x80
-#define CXL_VSEC_PROTOCOL_512TB  0x40
-#define CXL_VSEC_PROTOCOL_256TB  0x20 /* Power 8/9 uses this */
-#define CXL_VSEC_PROTOCOL_ENABLE 0x01
-
-#define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
-	pci_read_config_word(dev, vsec + 0xc, dest)
-#define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
-	pci_read_config_byte(dev, vsec + 0xe, dest)
-#define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
-	pci_read_config_byte(dev, vsec + 0xf, dest)
-#define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
-	pci_read_config_word(dev, vsec + 0x10, dest)
-
-#define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
-	pci_read_config_byte(dev, vsec + 0x13, dest)
-#define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
-	pci_write_config_byte(dev, vsec + 0x13, val)
-#define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
-#define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
-#define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
-
-#define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
-	pci_read_config_dword(dev, vsec + 0x20, dest)
-#define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
-	pci_read_config_dword(dev, vsec + 0x24, dest)
-#define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
-	pci_read_config_dword(dev, vsec + 0x28, dest)
-#define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
-	pci_read_config_dword(dev, vsec + 0x2c, dest)
-
-
-/* This works a little different than the p1/p2 register accesses to make it
- * easier to pull out individual fields */
-#define AFUD_READ(afu, off)		in_be64(afu->native->afu_desc_mmio + off)
-#define AFUD_READ_LE(afu, off)		in_le64(afu->native->afu_desc_mmio + off)
-#define EXTRACT_PPC_BIT(val, bit)	(!!(val & PPC_BIT(bit)))
-#define EXTRACT_PPC_BITS(val, bs, be)	((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
-
-#define AFUD_READ_INFO(afu)		AFUD_READ(afu, 0x0)
-#define   AFUD_NUM_INTS_PER_PROC(val)	EXTRACT_PPC_BITS(val,  0, 15)
-#define   AFUD_NUM_PROCS(val)		EXTRACT_PPC_BITS(val, 16, 31)
-#define   AFUD_NUM_CRS(val)		EXTRACT_PPC_BITS(val, 32, 47)
-#define   AFUD_MULTIMODE(val)		EXTRACT_PPC_BIT(val, 48)
-#define   AFUD_PUSH_BLOCK_TRANSFER(val)	EXTRACT_PPC_BIT(val, 55)
-#define   AFUD_DEDICATED_PROCESS(val)	EXTRACT_PPC_BIT(val, 59)
-#define   AFUD_AFU_DIRECTED(val)	EXTRACT_PPC_BIT(val, 61)
-#define   AFUD_TIME_SLICED(val)		EXTRACT_PPC_BIT(val, 63)
-#define AFUD_READ_CR(afu)		AFUD_READ(afu, 0x20)
-#define   AFUD_CR_LEN(val)		EXTRACT_PPC_BITS(val, 8, 63)
-#define AFUD_READ_CR_OFF(afu)		AFUD_READ(afu, 0x28)
-#define AFUD_READ_PPPSA(afu)		AFUD_READ(afu, 0x30)
-#define   AFUD_PPPSA_PP(val)		EXTRACT_PPC_BIT(val, 6)
-#define   AFUD_PPPSA_PSA(val)		EXTRACT_PPC_BIT(val, 7)
-#define   AFUD_PPPSA_LEN(val)		EXTRACT_PPC_BITS(val, 8, 63)
-#define AFUD_READ_PPPSA_OFF(afu)	AFUD_READ(afu, 0x38)
-#define AFUD_READ_EB(afu)		AFUD_READ(afu, 0x40)
-#define   AFUD_EB_LEN(val)		EXTRACT_PPC_BITS(val, 8, 63)
-#define AFUD_READ_EB_OFF(afu)		AFUD_READ(afu, 0x48)
-
-static const struct pci_device_id cxl_pci_tbl[] = {
-	{ PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
-	{ PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
-	{ PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
-	{ PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), },
-	{ PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0623), },
-	{ PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0628), },
-	{ }
-};
-MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
-
-
-/*
- * Mostly using these wrappers to avoid confusion:
- * priv 1 is BAR2, while priv 2 is BAR0
- */
-static inline resource_size_t p1_base(struct pci_dev *dev)
-{
-	return pci_resource_start(dev, 2);
-}
-
-static inline resource_size_t p1_size(struct pci_dev *dev)
-{
-	return pci_resource_len(dev, 2);
-}
-
-static inline resource_size_t p2_base(struct pci_dev *dev)
-{
-	return pci_resource_start(dev, 0);
-}
-
-static inline resource_size_t p2_size(struct pci_dev *dev)
-{
-	return pci_resource_len(dev, 0);
-}
-
-static int find_cxl_vsec(struct pci_dev *dev)
-{
-	return pci_find_vsec_capability(dev, PCI_VENDOR_ID_IBM, CXL_PCI_VSEC_ID);
-}
-
-static void dump_cxl_config_space(struct pci_dev *dev)
-{
-	int vsec;
-	u32 val;
-
-	dev_info(&dev->dev, "dump_cxl_config_space\n");
-
-	pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
-	dev_info(&dev->dev, "BAR0: %#.8x\n", val);
-	pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
-	dev_info(&dev->dev, "BAR1: %#.8x\n", val);
-	pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
-	dev_info(&dev->dev, "BAR2: %#.8x\n", val);
-	pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
-	dev_info(&dev->dev, "BAR3: %#.8x\n", val);
-	pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
-	dev_info(&dev->dev, "BAR4: %#.8x\n", val);
-	pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
-	dev_info(&dev->dev, "BAR5: %#.8x\n", val);
-
-	dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
-		p1_base(dev), p1_size(dev));
-	dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
-		p2_base(dev), p2_size(dev));
-	dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
-		pci_resource_start(dev, 4), pci_resource_len(dev, 4));
-
-	if (!(vsec = find_cxl_vsec(dev)))
-		return;
-
-#define show_reg(name, what) \
-	dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
-
-	pci_read_config_dword(dev, vsec + 0x0, &val);
-	show_reg("Cap ID", (val >> 0) & 0xffff);
-	show_reg("Cap Ver", (val >> 16) & 0xf);
-	show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
-	pci_read_config_dword(dev, vsec + 0x4, &val);
-	show_reg("VSEC ID", (val >> 0) & 0xffff);
-	show_reg("VSEC Rev", (val >> 16) & 0xf);
-	show_reg("VSEC Length",	(val >> 20) & 0xfff);
-	pci_read_config_dword(dev, vsec + 0x8, &val);
-	show_reg("Num AFUs", (val >> 0) & 0xff);
-	show_reg("Status", (val >> 8) & 0xff);
-	show_reg("Mode Control", (val >> 16) & 0xff);
-	show_reg("Reserved", (val >> 24) & 0xff);
-	pci_read_config_dword(dev, vsec + 0xc, &val);
-	show_reg("PSL Rev", (val >> 0) & 0xffff);
-	show_reg("CAIA Ver", (val >> 16) & 0xffff);
-	pci_read_config_dword(dev, vsec + 0x10, &val);
-	show_reg("Base Image Rev", (val >> 0) & 0xffff);
-	show_reg("Reserved", (val >> 16) & 0x0fff);
-	show_reg("Image Control", (val >> 28) & 0x3);
-	show_reg("Reserved", (val >> 30) & 0x1);
-	show_reg("Image Loaded", (val >> 31) & 0x1);
-
-	pci_read_config_dword(dev, vsec + 0x14, &val);
-	show_reg("Reserved", val);
-	pci_read_config_dword(dev, vsec + 0x18, &val);
-	show_reg("Reserved", val);
-	pci_read_config_dword(dev, vsec + 0x1c, &val);
-	show_reg("Reserved", val);
-
-	pci_read_config_dword(dev, vsec + 0x20, &val);
-	show_reg("AFU Descriptor Offset", val);
-	pci_read_config_dword(dev, vsec + 0x24, &val);
-	show_reg("AFU Descriptor Size", val);
-	pci_read_config_dword(dev, vsec + 0x28, &val);
-	show_reg("Problem State Offset", val);
-	pci_read_config_dword(dev, vsec + 0x2c, &val);
-	show_reg("Problem State Size", val);
-
-	pci_read_config_dword(dev, vsec + 0x30, &val);
-	show_reg("Reserved", val);
-	pci_read_config_dword(dev, vsec + 0x34, &val);
-	show_reg("Reserved", val);
-	pci_read_config_dword(dev, vsec + 0x38, &val);
-	show_reg("Reserved", val);
-	pci_read_config_dword(dev, vsec + 0x3c, &val);
-	show_reg("Reserved", val);
-
-	pci_read_config_dword(dev, vsec + 0x40, &val);
-	show_reg("PSL Programming Port", val);
-	pci_read_config_dword(dev, vsec + 0x44, &val);
-	show_reg("PSL Programming Control", val);
-
-	pci_read_config_dword(dev, vsec + 0x48, &val);
-	show_reg("Reserved", val);
-	pci_read_config_dword(dev, vsec + 0x4c, &val);
-	show_reg("Reserved", val);
-
-	pci_read_config_dword(dev, vsec + 0x50, &val);
-	show_reg("Flash Address Register", val);
-	pci_read_config_dword(dev, vsec + 0x54, &val);
-	show_reg("Flash Size Register", val);
-	pci_read_config_dword(dev, vsec + 0x58, &val);
-	show_reg("Flash Status/Control Register", val);
-	pci_read_config_dword(dev, vsec + 0x58, &val);
-	show_reg("Flash Data Port", val);
-
-#undef show_reg
-}
-
-static void dump_afu_descriptor(struct cxl_afu *afu)
-{
-	u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
-	int i;
-
-#define show_reg(name, what) \
-	dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
-
-	val = AFUD_READ_INFO(afu);
-	show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
-	show_reg("num_of_processes", AFUD_NUM_PROCS(val));
-	show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
-	show_reg("req_prog_mode", val & 0xffffULL);
-	afu_cr_num = AFUD_NUM_CRS(val);
-
-	val = AFUD_READ(afu, 0x8);
-	show_reg("Reserved", val);
-	val = AFUD_READ(afu, 0x10);
-	show_reg("Reserved", val);
-	val = AFUD_READ(afu, 0x18);
-	show_reg("Reserved", val);
-
-	val = AFUD_READ_CR(afu);
-	show_reg("Reserved", (val >> (63-7)) & 0xff);
-	show_reg("AFU_CR_len", AFUD_CR_LEN(val));
-	afu_cr_len = AFUD_CR_LEN(val) * 256;
-
-	val = AFUD_READ_CR_OFF(afu);
-	afu_cr_off = val;
-	show_reg("AFU_CR_offset", val);
-
-	val = AFUD_READ_PPPSA(afu);
-	show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
-	show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
-
-	val = AFUD_READ_PPPSA_OFF(afu);
-	show_reg("PerProcessPSA_offset", val);
-
-	val = AFUD_READ_EB(afu);
-	show_reg("Reserved", (val >> (63-7)) & 0xff);
-	show_reg("AFU_EB_len", AFUD_EB_LEN(val));
-
-	val = AFUD_READ_EB_OFF(afu);
-	show_reg("AFU_EB_offset", val);
-
-	for (i = 0; i < afu_cr_num; i++) {
-		val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
-		show_reg("CR Vendor", val & 0xffff);
-		show_reg("CR Device", (val >> 16) & 0xffff);
-	}
-#undef show_reg
-}
-
-#define P8_CAPP_UNIT0_ID 0xBA
-#define P8_CAPP_UNIT1_ID 0XBE
-#define P9_CAPP_UNIT0_ID 0xC0
-#define P9_CAPP_UNIT1_ID 0xE0
-
-static int get_phb_index(struct device_node *np, u32 *phb_index)
-{
-	if (of_property_read_u32(np, "ibm,phb-index", phb_index))
-		return -ENODEV;
-	return 0;
-}
-
-static u64 get_capp_unit_id(struct device_node *np, u32 phb_index)
-{
-	/*
-	 * POWER 8:
-	 *  - For chips other than POWER8NVL, we only have CAPP 0,
-	 *    irrespective of which PHB is used.
-	 *  - For POWER8NVL, assume CAPP 0 is attached to PHB0 and
-	 *    CAPP 1 is attached to PHB1.
-	 */
-	if (cxl_is_power8()) {
-		if (!pvr_version_is(PVR_POWER8NVL))
-			return P8_CAPP_UNIT0_ID;
-
-		if (phb_index == 0)
-			return P8_CAPP_UNIT0_ID;
-
-		if (phb_index == 1)
-			return P8_CAPP_UNIT1_ID;
-	}
-
-	/*
-	 * POWER 9:
-	 *   PEC0 (PHB0). Capp ID = CAPP0 (0b1100_0000)
-	 *   PEC1 (PHB1 - PHB2). No capi mode
-	 *   PEC2 (PHB3 - PHB4 - PHB5): Capi mode on PHB3 only. Capp ID = CAPP1 (0b1110_0000)
-	 */
-	if (cxl_is_power9()) {
-		if (phb_index == 0)
-			return P9_CAPP_UNIT0_ID;
-
-		if (phb_index == 3)
-			return P9_CAPP_UNIT1_ID;
-	}
-
-	return 0;
-}
-
-int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
-			     u32 *phb_index, u64 *capp_unit_id)
-{
-	int rc;
-	struct device_node *np;
-	u32 id;
-
-	if (!(np = pnv_pci_get_phb_node(dev)))
-		return -ENODEV;
-
-	while (np && of_property_read_u32(np, "ibm,chip-id", &id))
-		np = of_get_next_parent(np);
-	if (!np)
-		return -ENODEV;
-
-	*chipid = id;
-
-	rc = get_phb_index(np, phb_index);
-	if (rc) {
-		pr_err("cxl: invalid phb index\n");
-		of_node_put(np);
-		return rc;
-	}
-
-	*capp_unit_id = get_capp_unit_id(np, *phb_index);
-	of_node_put(np);
-	if (!*capp_unit_id) {
-		pr_err("cxl: No capp unit found for PHB[%lld,%d]. Make sure the adapter is on a capi-compatible slot\n",
-		       *chipid, *phb_index);
-		return -ENODEV;
-	}
-
-	return 0;
-}
-
-static DEFINE_MUTEX(indications_mutex);
-
-static int get_phb_indications(struct pci_dev *dev, u64 *capiind, u64 *asnind,
-			       u64 *nbwind)
-{
-	static u32 val[3];
-	struct device_node *np;
-
-	mutex_lock(&indications_mutex);
-	if (!val[0]) {
-		if (!(np = pnv_pci_get_phb_node(dev))) {
-			mutex_unlock(&indications_mutex);
-			return -ENODEV;
-		}
-
-		if (of_property_read_u32_array(np, "ibm,phb-indications", val, 3)) {
-			val[2] = 0x0300UL; /* legacy values */
-			val[1] = 0x0400UL;
-			val[0] = 0x0200UL;
-		}
-		of_node_put(np);
-	}
-	*capiind = val[0];
-	*asnind = val[1];
-	*nbwind = val[2];
-	mutex_unlock(&indications_mutex);
-	return 0;
-}
-
-int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg)
-{
-	u64 xsl_dsnctl;
-	u64 capiind, asnind, nbwind;
-
-	/*
-	 * CAPI Identifier bits [0:7]
-	 * bit 61:60 MSI bits --> 0
-	 * bit 59 TVT selector --> 0
-	 */
-	if (get_phb_indications(dev, &capiind, &asnind, &nbwind))
-		return -ENODEV;
-
-	/*
-	 * Tell XSL where to route data to.
-	 * The field chipid should match the PHB CAPI_CMPM register
-	 */
-	xsl_dsnctl = (capiind << (63-15)); /* Bit 57 */
-	xsl_dsnctl |= (capp_unit_id << (63-15));
-
-	/* nMMU_ID Defaults to: b’000001001’*/
-	xsl_dsnctl |= ((u64)0x09 << (63-28));
-
-	/*
-	 * Used to identify CAPI packets which should be sorted into
-	 * the Non-Blocking queues by the PHB. This field should match
-	 * the PHB PBL_NBW_CMPM register
-	 * nbwind=0x03, bits [57:58], must include capi indicator.
-	 * Not supported on P9 DD1.
-	 */
-	xsl_dsnctl |= (nbwind << (63-55));
-
-	/*
-	 * Upper 16b address bits of ASB_Notify messages sent to the
-	 * system. Need to match the PHB’s ASN Compare/Mask Register.
-	 * Not supported on P9 DD1.
-	 */
-	xsl_dsnctl |= asnind;
-
-	*reg = xsl_dsnctl;
-	return 0;
-}
-
-static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
-						 struct pci_dev *dev)
-{
-	u64 xsl_dsnctl, psl_fircntl;
-	u64 chipid;
-	u32 phb_index;
-	u64 capp_unit_id;
-	u64 psl_debug;
-	int rc;
-
-	rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
-	if (rc)
-		return rc;
-
-	rc = cxl_get_xsl9_dsnctl(dev, capp_unit_id, &xsl_dsnctl);
-	if (rc)
-		return rc;
-
-	cxl_p1_write(adapter, CXL_XSL9_DSNCTL, xsl_dsnctl);
-
-	/* Set fir_cntl to recommended value for production env */
-	psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
-	psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
-	psl_fircntl |= 0x1ULL; /* ce_thresh */
-	cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);
-
-	/* Setup the PSL to transmit packets on the PCIe before the
-	 * CAPP is enabled. Make sure that CAPP virtual machines are disabled
-	 */
-	cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0001001000012A10ULL);
-
-	/*
-	 * A response to an ASB_Notify request is returned by the
-	 * system as an MMIO write to the address defined in
-	 * the PSL_TNR_ADDR register.
-	 * keep the Reset Value: 0x00020000E0000000
-	 */
-
-	/* Enable XSL rty limit */
-	cxl_p1_write(adapter, CXL_XSL9_DEF, 0x51F8000000000005ULL);
-
-	/* Change XSL_INV dummy read threshold */
-	cxl_p1_write(adapter, CXL_XSL9_INV, 0x0000040007FFC200ULL);
-
-	if (phb_index == 3) {
-		/* disable machines 31-47 and 20-27 for DMA */
-		cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000FF3FFFF0000ULL);
-	}
-
-	/* Snoop machines */
-	cxl_p1_write(adapter, CXL_PSL9_APCDEDALLOC, 0x800F000200000000ULL);
-
-	/* Enable NORST and DD2 features */
-	cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0xC000000000000000ULL);
-
-	/*
-	 * Check if PSL has data-cache. We need to flush adapter datacache
-	 * when as its about to be removed.
-	 */
-	psl_debug = cxl_p1_read(adapter, CXL_PSL9_DEBUG);
-	if (psl_debug & CXL_PSL_DEBUG_CDC) {
-		dev_dbg(&dev->dev, "No data-cache present\n");
-		adapter->native->no_data_cache = true;
-	}
-
-	return 0;
-}
-
-static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci_dev *dev)
-{
-	u64 psl_dsnctl, psl_fircntl;
-	u64 chipid;
-	u32 phb_index;
-	u64 capp_unit_id;
-	int rc;
-
-	rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
-	if (rc)
-		return rc;
-
-	psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
-	psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
-	/* Tell PSL where to route data to */
-	psl_dsnctl |= (chipid << (63-5));
-	psl_dsnctl |= (capp_unit_id << (63-13));
-
-	cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
-	cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
-	/* snoop write mask */
-	cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
-	/* set fir_cntl to recommended value for production env */
-	psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
-	psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
-	psl_fircntl |= 0x1ULL; /* ce_thresh */
-	cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl);
-	/* for debugging with trace arrays */
-	cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
-
-	return 0;
-}
-
-/* PSL */
-#define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3))
-#define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
-/* For the PSL this is a multiple for 0 < n <= 7: */
-#define PSL_2048_250MHZ_CYCLES 1
-
-static void write_timebase_ctrl_psl8(struct cxl *adapter)
-{
-	cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
-		     TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
-}
-
-static u64 timebase_read_psl9(struct cxl *adapter)
-{
-	return cxl_p1_read(adapter, CXL_PSL9_Timebase);
-}
-
-static u64 timebase_read_psl8(struct cxl *adapter)
-{
-	return cxl_p1_read(adapter, CXL_PSL_Timebase);
-}
-
-static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
-{
-	struct device_node *np;
-
-	adapter->psl_timebase_synced = false;
-
-	if (!(np = pnv_pci_get_phb_node(dev)))
-		return;
-
-	/* Do not fail when CAPP timebase sync is not supported by OPAL */
-	of_node_get(np);
-	if (!of_property_present(np, "ibm,capp-timebase-sync")) {
-		of_node_put(np);
-		dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n");
-		return;
-	}
-	of_node_put(np);
-
-	/*
-	 * Setup PSL Timebase Control and Status register
-	 * with the recommended Timebase Sync Count value
-	 */
-	if (adapter->native->sl_ops->write_timebase_ctrl)
-		adapter->native->sl_ops->write_timebase_ctrl(adapter);
-
-	/* Enable PSL Timebase */
-	cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
-	cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
-
-	return;
-}
-
-static int init_implementation_afu_regs_psl9(struct cxl_afu *afu)
-{
-	return 0;
-}
-
-static int init_implementation_afu_regs_psl8(struct cxl_afu *afu)
-{
-	/* read/write masks for this slice */
-	cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
-	/* APC read/write masks for this slice */
-	cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
-	/* for debugging with trace arrays */
-	cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
-	cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
-
-	return 0;
-}
-
-int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq,
-		unsigned int virq)
-{
-	struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
-
-	return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
-}
-
-int cxl_update_image_control(struct cxl *adapter)
-{
-	struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
-	int rc;
-	int vsec;
-	u8 image_state;
-
-	if (!(vsec = find_cxl_vsec(dev))) {
-		dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
-		return -ENODEV;
-	}
-
-	if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
-		dev_err(&dev->dev, "failed to read image state: %i\n", rc);
-		return rc;
-	}
-
-	if (adapter->perst_loads_image)
-		image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
-	else
-		image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
-
-	if (adapter->perst_select_user)
-		image_state |= CXL_VSEC_PERST_SELECT_USER;
-	else
-		image_state &= ~CXL_VSEC_PERST_SELECT_USER;
-
-	if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
-		dev_err(&dev->dev, "failed to update image control: %i\n", rc);
-		return rc;
-	}
-
-	return 0;
-}
-
-int cxl_pci_alloc_one_irq(struct cxl *adapter)
-{
-	struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
-
-	return pnv_cxl_alloc_hwirqs(dev, 1);
-}
-
-void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq)
-{
-	struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
-
-	return pnv_cxl_release_hwirqs(dev, hwirq, 1);
-}
-
-int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
-			struct cxl *adapter, unsigned int num)
-{
-	struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
-
-	return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
-}
-
-void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs,
-				struct cxl *adapter)
-{
-	struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
-
-	pnv_cxl_release_hwirq_ranges(irqs, dev);
-}
-
-static int setup_cxl_bars(struct pci_dev *dev)
-{
-	/* Safety check in case we get backported to < 3.17 without M64 */
-	if ((p1_base(dev) < 0x100000000ULL) ||
-	    (p2_base(dev) < 0x100000000ULL)) {
-		dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
-		return -ENODEV;
-	}
-
-	/*
-	 * BAR 4/5 has a special meaning for CXL and must be programmed with a
-	 * special value corresponding to the CXL protocol address range.
-	 * For POWER 8/9 that means bits 48:49 must be set to 10
-	 */
-	pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
-	pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
-
-	return 0;
-}
-
-/* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */
-static int switch_card_to_cxl(struct pci_dev *dev)
-{
-	int vsec;
-	u8 val;
-	int rc;
-
-	dev_info(&dev->dev, "switch card to CXL\n");
-
-	if (!(vsec = find_cxl_vsec(dev))) {
-		dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
-		return -ENODEV;
-	}
-
-	if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) {
-		dev_err(&dev->dev, "failed to read current mode control: %i", rc);
-		return rc;
-	}
-	val &= ~CXL_VSEC_PROTOCOL_MASK;
-	val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
-	if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) {
-		dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc);
-		return rc;
-	}
-	/*
-	 * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states
-	 * we must wait 100ms after this mode switch before touching
-	 * PCIe config space.
-	 */
-	msleep(100);
-
-	return 0;
-}
-
-static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
-{
-	u64 p1n_base, p2n_base, afu_desc;
-	const u64 p1n_size = 0x100;
-	const u64 p2n_size = 0x1000;
-
-	p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
-	p2n_base = p2_base(dev) + (afu->slice * p2n_size);
-	afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
-	afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
-
-	if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size)))
-		goto err;
-	if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
-		goto err1;
-	if (afu_desc) {
-		if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size)))
-			goto err2;
-	}
-
-	return 0;
-err2:
-	iounmap(afu->p2n_mmio);
-err1:
-	iounmap(afu->native->p1n_mmio);
-err:
-	dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
-	return -ENOMEM;
-}
-
-static void pci_unmap_slice_regs(struct cxl_afu *afu)
-{
-	if (afu->p2n_mmio) {
-		iounmap(afu->p2n_mmio);
-		afu->p2n_mmio = NULL;
-	}
-	if (afu->native->p1n_mmio) {
-		iounmap(afu->native->p1n_mmio);
-		afu->native->p1n_mmio = NULL;
-	}
-	if (afu->native->afu_desc_mmio) {
-		iounmap(afu->native->afu_desc_mmio);
-		afu->native->afu_desc_mmio = NULL;
-	}
-}
-
-void cxl_pci_release_afu(struct device *dev)
-{
-	struct cxl_afu *afu = to_cxl_afu(dev);
-
-	pr_devel("%s\n", __func__);
-
-	idr_destroy(&afu->contexts_idr);
-	cxl_release_spa(afu);
-
-	kfree(afu->native);
-	kfree(afu);
-}
-
-/* Expects AFU struct to have recently been zeroed out */
-static int cxl_read_afu_descriptor(struct cxl_afu *afu)
-{
-	u64 val;
-
-	val = AFUD_READ_INFO(afu);
-	afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
-	afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
-	afu->crs_num = AFUD_NUM_CRS(val);
-
-	if (AFUD_AFU_DIRECTED(val))
-		afu->modes_supported |= CXL_MODE_DIRECTED;
-	if (AFUD_DEDICATED_PROCESS(val))
-		afu->modes_supported |= CXL_MODE_DEDICATED;
-	if (AFUD_TIME_SLICED(val))
-		afu->modes_supported |= CXL_MODE_TIME_SLICED;
-
-	val = AFUD_READ_PPPSA(afu);
-	afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
-	afu->psa = AFUD_PPPSA_PSA(val);
-	if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
-		afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu);
-
-	val = AFUD_READ_CR(afu);
-	afu->crs_len = AFUD_CR_LEN(val) * 256;
-	afu->crs_offset = AFUD_READ_CR_OFF(afu);
-
-
-	/* eb_len is in multiple of 4K */
-	afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
-	afu->eb_offset = AFUD_READ_EB_OFF(afu);
-
-	/* eb_off is 4K aligned so lower 12 bits are always zero */
-	if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
-		dev_warn(&afu->dev,
-			 "Invalid AFU error buffer offset %Lx\n",
-			 afu->eb_offset);
-		dev_info(&afu->dev,
-			 "Ignoring AFU error buffer in the descriptor\n");
-		/* indicate that no afu buffer exists */
-		afu->eb_len = 0;
-	}
-
-	return 0;
-}
-
-static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
-{
-	int i, rc;
-	u32 val;
-
-	if (afu->psa && afu->adapter->ps_size <
-			(afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
-		dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
-		return -ENODEV;
-	}
-
-	if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
-		dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size);
-
-	for (i = 0; i < afu->crs_num; i++) {
-		rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
-		if (rc || val == 0) {
-			dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
-			return -EINVAL;
-		}
-	}
-
-	if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) {
-		/*
-		 * We could also check this for the dedicated process model
-		 * since the architecture indicates it should be set to 1, but
-		 * in that case we ignore the value and I'd rather not risk
-		 * breaking any existing dedicated process AFUs that left it as
-		 * 0 (not that I'm aware of any). It is clearly an error for an
-		 * AFU directed AFU to set this to 0, and would have previously
-		 * triggered a bug resulting in the maximum not being enforced
-		 * at all since idr_alloc treats 0 as no maximum.
-		 */
-		dev_err(&afu->dev, "AFU does not support any processes\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int sanitise_afu_regs_psl9(struct cxl_afu *afu)
-{
-	u64 reg;
-
-	/*
-	 * Clear out any regs that contain either an IVTE or address or may be
-	 * waiting on an acknowledgment to try to be a bit safer as we bring
-	 * it online
-	 */
-	reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
-	if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
-		dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
-		if (cxl_ops->afu_reset(afu))
-			return -EIO;
-		if (cxl_afu_disable(afu))
-			return -EIO;
-		if (cxl_psl_purge(afu))
-			return -EIO;
-	}
-	cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
-	cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
-	reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
-	if (reg) {
-		dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
-		if (reg & CXL_PSL9_DSISR_An_TF)
-			cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
-		else
-			cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
-	}
-	if (afu->adapter->native->sl_ops->register_serr_irq) {
-		reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
-		if (reg) {
-			if (reg & ~0x000000007fffffff)
-				dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
-			cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
-		}
-	}
-	reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
-	if (reg) {
-		dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
-		cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
-	}
-
-	return 0;
-}
-
-static int sanitise_afu_regs_psl8(struct cxl_afu *afu)
-{
-	u64 reg;
-
-	/*
-	 * Clear out any regs that contain either an IVTE or address or may be
-	 * waiting on an acknowledgement to try to be a bit safer as we bring
-	 * it online
-	 */
-	reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
-	if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
-		dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
-		if (cxl_ops->afu_reset(afu))
-			return -EIO;
-		if (cxl_afu_disable(afu))
-			return -EIO;
-		if (cxl_psl_purge(afu))
-			return -EIO;
-	}
-	cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
-	cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
-	cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
-	cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
-	cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
-	cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
-	cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
-	cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
-	cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
-	cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
-	cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
-	reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
-	if (reg) {
-		dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
-		if (reg & CXL_PSL_DSISR_TRANS)
-			cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
-		else
-			cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
-	}
-	if (afu->adapter->native->sl_ops->register_serr_irq) {
-		reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
-		if (reg) {
-			if (reg & ~0xffff)
-				dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
-			cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
-		}
-	}
-	reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
-	if (reg) {
-		dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
-		cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
-	}
-
-	return 0;
-}
-
-#define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
-/*
- * afu_eb_read:
- * Called from sysfs and reads the afu error info buffer. The h/w only supports
- * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte
- * aligned the function uses a bounce buffer which can be max PAGE_SIZE.
- */
-ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
-				loff_t off, size_t count)
-{
-	loff_t aligned_start, aligned_end;
-	size_t aligned_length;
-	void *tbuf;
-	const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
-
-	if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
-		return 0;
-
-	/* calculate aligned read window */
-	count = min((size_t)(afu->eb_len - off), count);
-	aligned_start = round_down(off, 8);
-	aligned_end = round_up(off + count, 8);
-	aligned_length = aligned_end - aligned_start;
-
-	/* max we can copy in one read is PAGE_SIZE */
-	if (aligned_l