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| author | Oleksij Rempel <o.rempel@pengutronix.de> | 2022-12-05 06:22:30 +0100 |
|---|---|---|
| committer | Paolo Abeni <pabeni@redhat.com> | 2022-12-07 11:57:58 +0100 |
| commit | 29d1e85f45e03c9fd1b8985f983f33c021e130c8 (patch) | |
| tree | e4f31b4ba722611b104da68357916df154068a44 /drivers/net/dsa/microchip/ksz8795_reg.h | |
| parent | 6f1b986a43ce9aa67b11a7e54ac75530705d04e7 (diff) | |
| download | linux-29d1e85f45e03c9fd1b8985f983f33c021e130c8.tar.gz linux-29d1e85f45e03c9fd1b8985f983f33c021e130c8.tar.bz2 linux-29d1e85f45e03c9fd1b8985f983f33c021e130c8.zip | |
net: dsa: microchip: ksz8: add MTU configuration support
Make MTU configurable on KSZ87xx and KSZ88xx series of switches.
Before this patch, pre-configured behavior was different on different
switch series, due to opposite meaning of the same bit:
- KSZ87xx: Reg 4, Bit 1 - if 1, max frame size is 1532; if 0 - 1514
- KSZ88xx: Reg 4, Bit 1 - if 1, max frame size is 1514; if 0 - 1532
Since the code was telling "... SW_LEGAL_PACKET_DISABLE, true)", I
assume, the idea was to set max frame size to 1532.
With this patch, by setting MTU size 1500, both switch series will be
configured to the 1532 frame limit.
This patch was tested on KSZ8873.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Acked-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Diffstat (limited to 'drivers/net/dsa/microchip/ksz8795_reg.h')
| -rw-r--r-- | drivers/net/dsa/microchip/ksz8795_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/dsa/microchip/ksz8795_reg.h b/drivers/net/dsa/microchip/ksz8795_reg.h index 77487d611824..7a57c6088f80 100644 --- a/drivers/net/dsa/microchip/ksz8795_reg.h +++ b/drivers/net/dsa/microchip/ksz8795_reg.h @@ -48,6 +48,9 @@ #define NO_EXC_COLLISION_DROP BIT(3) #define SW_LEGAL_PACKET_DISABLE BIT(1) +#define KSZ8863_HUGE_PACKET_ENABLE BIT(2) +#define KSZ8863_LEGAL_PACKET_ENABLE BIT(1) + #define REG_SW_CTRL_3 0x05 #define WEIGHTED_FAIR_QUEUE_ENABLE BIT(3) |